Jump to content

Alpha 21066A

From Alfawiki
Digital Equipment Corporation
IndustryComputer hardware
FoundedNovember 7, 1957; 69 years ago (1957-11-07)
Headquarters
Maynard, Massachusetts
,
United States
ProductsAlpha 21064 microprocessor, DECchip series, workstations, servers

The Alpha 21064 is a microprocessor created and produced by Digital Equipment Corporation that implements the Alpha (initially known as Alpha AXP) instruction set architecture (ISA). Originally launched as the DECchip 21064, it was rebranded in 1994. Internally referred to as EV4, this processor made its first appearance in February 1992, with mass production starting in September of the same year. The 21064 marked Digital's inaugural commercial Alpha microprocessor. It was later succeeded by the Alpha 21064A in October 1993, which itself was followed by the Alpha 21164 in 1995.

History

The first Alpha processor was a prototype chip, designated EV3, manufactured using Digital's 1.0-micrometre (μm) CMOS-3 technology. This early version did not include a floating point unit and featured only 1 KB caches. Its purpose was to validate advanced circuit design methods and facilitate firmware and operating system development.

The production-ready chip, known as EV4, employed Digital's 0.75 μm CMOS-4 fabrication process. The design team was led by micro-architects Dirk Meyer and Edward McLellan, with Jim Montanaro overseeing circuit implementation. Prior to EV4’s availability, the EV3 powered the Alpha Demonstration Unit (ADU), a multiprocessor platform used for software development.

Introduced at the 39th International Solid-State Circuits Conference (ISSCC) in February 1992, the initial 150 MHz samples were priced at $3,375 each for orders over 100 units, decreasing to $1,560 at volumes exceeding 1,000 units. Full-scale shipments commenced in September 1992.

By early 1993, the price for the 150 MHz model had dropped to $1,096 per unit for orders above 1,000. On February 25, 1993, a faster 200 MHz variant was launched with a sample price of $3,495 and volume pricing of $1,231 for orders over 10,000 units, with shipping beginning in August. This release prompted a corresponding price reduction for the original 150 MHz model.

Following the introduction of the Alpha 21066 and 21068 models in September 1993, Digital adjusted its product lineup and added a 166 MHz version priced at $499 per unit for orders exceeding 5,000 units, while lowering the cost of the 150 MHz variant to $455.

On June 6, 1994, further price cuts were implemented: the 200 MHz version saw a reduction of 31% to $544 per unit, and the 166 MHz model decreased by 19% to $404 per unit (for orders over 5,000), enhancing competitiveness against Intel’s Pentium processors.

Digital Equipment Corporation was the exclusive manufacturer of the Alpha 21064 with no secondary production sources. Manufacturing took place at Digital’s semiconductor facilities located in Hudson, Massachusetts and South Queensferry, Scotland.

Users

The primary applications of the 21064 were in high-performance workstations and server systems. Notable adopters included:

Performance

When it debuted, the 21064 was the fastest microprocessor available until IBM introduced the multi-chip POWER2 in 1993. It held the title of highest-performing single-chip processor until the arrival of the 275 MHz 21064A in October 1993.

Description

The Alpha 21064 is a superpipelined and dual-issue superscalar CPU that processes instructions sequentially. It can dispatch up to two instructions per clock cycle across four execution units: integer, floating-point (FPU), address, and branch units. The integer pipeline consists of seven stages, while the floating-point pipeline extends to ten stages; both share the initial four stages managed by the I-box.

I-box

Functioning as the control hub, the I-box is responsible for instruction fetching, decoding, issuing, and pipeline control. At the first stage, it retrieves two instructions from the instruction cache (I-cache). Branch prediction takes place in stage two through either static or dynamic techniques: static prediction assesses the sign bit of the branch displacement (predicting taken if backward), whereas dynamic prediction utilizes a 2,048-entry branch history table achieving approximately 80% accuracy. Incorrect branch predictions incur a penalty of four cycles.

Instruction decoding happens at stage three. By stage four, the I-box checks resource availability to issue instruction pairs. The 21064 can pair instructions such as integer operate with floating-point operate, load/store with operate, integer operate with integer branch, or floating-point operate with floating-point branch. However, pairing an integer operate with a floating-point store or a floating-point operate with an integer store is not supported. If pairing cannot be performed due to resource constraints, stages one through four stall until conditions permit issuing.

The I-box contains two fully associative instruction translation buffers (ITBs) for converting virtual addresses to physical addresses: an eight-entry ITB dedicated to 8 KB pages and a four-entry ITB for 4 MB pages, both employing a not-last used replacement strategy.

Execution

All instructions commence execution at stage five, with register file reads occurring in stage four. Pipelines beginning at this point are designed to run without stalls.

Integer unit

The integer unit processes integer instructions and comprises the integer register file (IRF) along with the E-box. The IRF includes thirty-two 64-bit registers featuring four read ports and two write ports shared between integer and branch units. The E-box incorporates an adder, logic unit, barrel shifter, and multiplier. Except for multiply, shift, and byte manipulation instructions, most integer operations complete by stage five with a one-cycle latency. Shift and byte manipulation instructions require two cycles due to pipeline timing constraints. To conserve die space, the multiplier is not pipelined and exhibits variable latency ranging from 19 to 23 cycles. Integer results are written back to the IRF during stage seven.

Address unit

The address unit ("A-box") executes load and store operations. It features a dedicated displacement adder that allows it to function concurrently with the integer unit. Virtual-to-physical address translation is handled by a 32-entry fully associative translation lookaside buffer (TLB) known as the data translation buffer (DTB). The processor supports a virtual address space of 43 bits (8 TB) and a physical address space of 34 bits (16 GB).

For store operations, a write buffer consisting of four entries each holding 32 bytes improves efficiency by combining adjacent stores and deferring writebacks. This mechanism reduces system bus traffic and accelerates load access times.

Floating-point unit

The floating-point unit integrates the floating-point register file (FRF), consisting of thirty-two 64-bit registers equipped with three read ports and two write ports, alongside the F-box. The F-box incorporates a floating-point pipeline and a non-pipelined division unit that completes one bit per cycle.

During the fourth stage, data is retrieved from the FRF and decomposed into fraction, exponent, and sign components. For addition instructions, the difference between exponents is computed and normalization begins; for multiplication, a 3 × multiplicand is generated.

Stages five and six handle alignment or normalization shifts as well as sticky-bit computation for addition and subtraction operations. Multiplication employs a pipelined, two-way interleaved array utilizing a radix-8 Booth algorithm. Final addition and rounding are executed in stage eight, with results written back to the FRF at stage ten.

The latency of the floating-point pipeline is six cycles. In contrast, non-pipelined division operations have latencies of 31 cycles for single-precision and 61 cycles for double-precision.

Caches

The 21064 incorporates two on-chip primary caches: an 8 KB data cache (D-cache) with a write-through policy and an 8 KB instruction cache (I-cache). Both caches are direct-mapped to enable single-cycle access and feature 32-byte line sizes. Constructed using six-transistor SRAM cells, each cache array is 1,024 cells wide by 66 cells high, with redundant rows incorporated at the top.

An optional external secondary cache (B-cache) was supported, ranging from 128 KB up to 16 MB in size. This B-cache operates at frequencies between one-third and one-sixteenth of the internal clock rate (12.5 to 66.67 MHz at a 200 MHz internal clock), is direct-mapped with a default line size of 128 bytes, and interfaces via the system bus.

External interface

The external interface provides a configurable data bus width of 128 bits, functioning at speeds from half to one-eighth of the internal clock frequency (25 to 100 MHz at a 200 MHz core clock), although some implementations use a 64-bit bus. Additionally, it includes a 34-bit address bus.

Fabrication

The 21064 chip comprises approximately 1.68 million transistors and was originally manufactured using Digital’s CMOS-4 process technology featuring a 0.75 μm minimum feature size and three levels of aluminum interconnect. The initial EV4 die measured 13.9 mm by 16.8 mm (233.52 mm²). The EV4S variant employed CMOS-4S technology, representing a 10% optical shrink to 0.675 μm dimensions, reducing die size to 12.4 mm by 15.0 mm (186 mm²).

Operating on a 3.3-volt power supply, the EV4 consumed up to 30 W at 200 MHz. The EV4S improved power efficiency, dissipating between 21 W at 150 MHz and up to 27 W at full speed of 200 MHz.

Package

The processor is enclosed in a pin grid array (PGA) package made from alumina ceramic, measuring 61.72 mm square with a total of 431 pins. Of these pins, 291 are allocated for signal transmission while the remaining 140 provide power and ground connections. The heatsink mounts directly onto the package and is secured by studs attached to a tungsten heat spreader.

Alpha 21064A

The Alpha 21064A, also known as the DECchip 21064A or by its codename EV45, represents an upgraded iteration of the Alpha 21064 introduced in October 1993. It was available at clock rates of 200, 225, 233, 275, and 300 MHz. The model running at 225 MHz was superseded by the 233 MHz version on July 6, 1994, which was priced at US$788 per unit when purchased in quantities of five thousand—marking a price reduction of approximately ten percent compared to its predecessor. On that same date, the cost of the 275 MHz variant fell by twenty-five percent to US$1,083. The fastest model at 300 MHz was announced in October 1995 and began shipping by December that year. A specialized variant named the 21064A-275-PC was produced exclusively for running Windows NT or compatible operating systems.

As Digital’s premier high-performance microprocessor, the Alpha 21064A powered several high-end systems including:

  • Digital’s DEC 3000 AXP, DEC 4000 AXP, and DEC 7000/10000 AXP series
  • Aspen Systems’ Alpine workstation
  • BTG’s Action AXP275 RISC PC (275 MHz configuration)
  • Carrera Computers’ Cobra AXP 275 workstation
  • NekoTech’s Mach 2-289-T workstation (overclocked to 289 MHz)
  • NetApp storage solutions (275 MHz version)

Architectural enhancements featured doubling both primary I-cache and D-cache sizes from eight to sixteen kilobytes with parity protection added, improved floating-point divide performance through an optimized divider design reducing latency, and an expanded branch history table containing 4,096 entries utilizing two-bit prediction schemes. The chip integrates approximately 2.8 million transistors on a die measuring roughly 152.25 mm2, fabricated using Digital’s CMOS-5 process technology which uses a 0.5 μm feature size along with four layers of aluminum interconnects.

Alpha 21066

The Alpha 21066, also known as the DECchip 21066 and internally referred to as LCA4 (Low Cost Alpha), represents an economical version of the Alpha processor architecture. Initial samples were released in September 1993, with mass production commencing in early 1994. The first variant operated at 166 MHz and was priced at approximately US$385 per unit when purchased in lots of 5,000. A lower-frequency, energy-efficient 100 MHz model aimed at embedded applications began sampling in late 1994 and reached the market by the third quarter of 1995. This processor was distinguished by being the first to integrate a PCI controller on-chip.

Primarily engineered for budget-conscious uses—particularly personal computers running Windows NT—the Alpha 21066 found its way into Digital’s Multia client systems, AXPpci33 OEM motherboards, and AXPvme single-board computers. Additional adopters comprised Aspen Systems’ Alpine workstation, Carrera Computers’ Pantera I workstation, NekoTech’s Mach 1-166 PC, and Parsys’ TransAlpha TA9000 supercomputers.

Taking advantage of process miniaturization, the chip combined a B-cache and memory controller with ECC capabilities, a basic graphics accelerator supporting up to 8 MB of VRAM for framebuffer operations, an integrated PCI controller, and a PLL clock multiplier that converted a 33 MHz external clock into higher internal frequencies.

Its memory controller accommodated B-cache sizes ranging from 64 KB up to 2 MB and system memory capacities between 2 and 512 MB. The ECC functionality detected multi-bit errors while correcting single-bit faults. To further reduce manufacturing expenses, the system bus width was scaled down to 64 bits—this design choice lowered pin count and package dimensions but resulted in roughly a 20% performance reduction, which was deemed acceptable for its intended applications.

The processor contained approximately 1.75 million transistors on a die measuring 209.1 mm2 (17.0 ×12.3 mm). Fabricated using CMOS-4S technology—a 0.675 μm process featuring three layers of interconnect—the chip was housed in a sizable 287-pin CPGA package measuring 57.404 ×57.404 mm.

Alpha 21066A

The Alpha 21066A, codenamed LCA45, serves as a cost-effective iteration of the Alpha 21064A. It was announced on November 14, 1994, with models operating at 100 and 233 MHz becoming available in March 1995. The initial pricing stood at $175 for the lower-speed model and $360 for the higher-speed version when bought in batches of 5,000 units; subsequently, a faster 266 MHz variant was introduced.

Mitsubishi Electric acted as a second source for the 21066A under the designation M36066A, marking its inaugural production of an Alpha microprocessor. Announced concurrently with Digital's versions, Mitsubishi planned to provide engineering samples by December 1994 and commence volume manufacturing by September 1995, pricing the 233 MHz chip at $490 per thousand units.

Differing from the 21064A, the 21066A excluded the separate 16 KB instruction and data caches but incorporated software-controlled power management features that allowed adjustment of internal clock frequencies for efficiency. Digital utilized various configurations of the 21066A in systems that had previously employed the original 21066, while Tadpole Technology integrated a 233 MHz model into its ALPHAbook 1 laptop.

This processor contained approximately 1.8 million transistors on a die measuring 161.32 mm2, manufactured using Digital's CMOS-5 process (0.5 μm), whereas Mitsubishi fabricated their M36066A version using a comparable process technology.

Alpha 21068

The Alpha 21068 (DECchip 21068) was designed specifically for embedded applications, closely resembling the architecture of the Alpha 21066 but operating at a reduced frequency of 66 MHz to minimize power consumption and cost. Released in September 1993 with volume shipments beginning early in 1994, it featured a maximum power dissipation rating of only 9 watts and was initially priced at $221 per unit for orders of 5,000 pieces—later reduced by about sixteen percent to $186.

Digital incorporated the Alpha 21068 into its AXPpci33 motherboard as well as AXPvme single-board computer products.

Alpha 21068A

The Alpha 21068A (also known as DECchip 21068A) is a specialized embedded version of the Alpha 21066A processor, operating at a clock speed of 100 MHz.

Chipsets

At first, the 21064 and 21064A processors did not have an associated standard chipset, prompting Digital to utilize proprietary ASICs for processor interfacing. To lower the development burden for original equipment manufacturers (OEMs), Digital launched the DECchip 21070 chipset, codenamed Apecs.

The DECchip 21070 was offered in two variants: the 21071, designed for workstation use, and the 21072, aimed at high-performance workstations or entry-level uniprocessor servers. Their primary distinction was in memory architecture—the 21071 supported a 64-bit memory bus with parity-protected memory ranging from 8 MB up to 2 GB, while the 21072 featured a wider 128-bit memory bus capable of handling up to 4 GB of ECC-protected memory.

This chipset consisted of three main elements: the COMANCHE B-cache and memory controller, DECADE data slices (two slices for the 21071 and four for the 21072), and the EPIC PCI controller, which connected through a 32-bit interface.

Announced on January 10, 1994, samples were made available shortly thereafter, with mass production starting mid-year. Pricing at volumes of 5,000 units was set at $90 for the 21071 and $120 for the 21072.

Among its adopters were Carrera Computers for their Pantera workstation line and Digital itself for select AlphaStation models as well as some uniprocessor AlphaServer configurations.

References

Further reading

  • "DEC Ventures into Microprocessor Market with Alpha". (4 March 1992). Microprocessor Report, Volume 6, Number 3.
  • "Introduction of DEC's Alpha Architecture". (4 March 1992). Microprocessor Report, Volume 6, Number 3.
  • "Digital Unveils Extensive Alpha Processor Lineup". (18 November 1992). Microprocessor Report, Volume 6, Number 3.
  • "Digital Announces PCI Chip Sets for Alpha Processors". (12 July 1993). Microprocessor Report, Volume 7, Number 9.
  • "Alpha Expands to Entry-Level with Digital's 21066 Model". (13 September 1993). Microprocessor Report, Volume 7, Number 12.
  • Bhandarkar, Dileep P. (1995). Alpha Architecture and Implementations. Digital Press.
  • Fox, Thomas F. (1994). "Designing High-Performance Microprocessors at Digital". Proceedings of the 31st Annual ACM-IEEE Design Automation Conference. pp. 586–591.
  • Gronowski, Paul E. et al. (May 1998). "Designing High-Performance Microprocessors". IEEE Journal of Solid-State Circuits 33 (5): pp. 676–686.

de:Alpha-Prozessor#Benennung

Retrieved from "https://www.alfawiki.org/index.php?title=Alpha_21066A&oldid=22791"