CDC Cyber

Control Data Corporation
Industry	Computer hardware, Supercomputers
Founded	January 1, 1957; 69 years ago
Headquarters	Minneapolis, United States
Products	CDC Cyber series of supercomputers, Cyber 18 and Cyber 1000 minicomputers

The CDC Cyber series of mainframe-level supercomputers represented the premier offerings from Control Data Corporation (CDC) throughout the 1970s and 1980s. These machines were highly regarded for tasks demanding extensive scientific and mathematical computation, including applications such as fluid dynamics simulation, stress testing of materials, electrochemical machining processes, probabilistic modeling, energy sector research, academic computing environments, and radiation shielding design. The product range also encompassed the Cyber 18 and Cyber 1000 minicomputer models. Similar to their predecessor, the CDC 6600, these systems utilized the relatively rare ones' complement binary number format.

Models

The Cyber family consisted of five distinct series:

The 70 and 170 series, which were architecturally based on the CDC 6600 and CDC 7600 supercomputers
The 200 series, which evolved from the CDC STAR-100 platform introduced in the 1970s
The 180 series, developed in Canada and launched during the 1980s following the 200 series
The Cyberplus or Advanced Flexible Processor (AFP)
The Cyber 18 minicomputer, derived from the CDC 1700

Although primarily designed for large-scale office workloads rather than conventional supercomputing applications, select Cyber models incorporated fundamental vector instruction capabilities to boost performance within CDC’s primary scientific computing markets.

Cyber 70 and 170 series

The Cyber 70 and 170 series succeeded the CDC 6600 and CDC 7600, maintaining much of their architectural design. The Cyber-70 series represented a modest enhancement: for example, the Cyber-73—resembling the CDC 6400—introduced a Compare and Move Unit (CMU) to accelerate processing of unaligned six-bit character data. It supported configurations with one or two CPUs, with the dual-CPU variant replacing the CDC 6500. The Cyber-72 shared identical hardware with the Cyber-73 but operated at a slower clock speed by inserting additional cycles, offering a more economical option without hardware redesign. The Cyber-74 was an update to the CDC 6600, while the Cyber-76 was essentially a rebranded CDC 7600; neither model incorporated CMU instructions.

The Cyber-170 series marked CDC’s shift from discrete componentry and core memory technology to integrated circuits and semiconductor memory. Models such as the 172, 173, and 174 utilized integrated circuits, whereas the 175 employed high-speed discrete transistor technology. This lineup was refreshed in the late 1970s with the introduction of the Cyber-170/700 series.

Both central processors and main memory operated on a word size of 60 bits; CDC defined its "byte" as a twelve-bit unit aligned with peripheral processors. Characters and operation codes used six bits each; central memory addressing was limited to eighteen bits, restricting main memory capacity to a maximum of 256K words of semiconductor memory. CPUs did not contain I/O instructions themselves; input/output operations were delegated entirely to peripheral processors (PPs).

A typical configuration of a Cyber 170 system included one or two CPUs running at either 25 or 40 MHz, accompanied by between ten and twenty peripheral processors plus up to twenty-four high-speed I/O channels. Because memory access times were relatively slow—sometimes exceeding floating-point divide durations—the higher-end CPUs (Cyber-74, -76, -175, -176) incorporated an instruction cache ("in-stack") holding eight to twelve words for rapid loop execution without accessing main memory. Lower-end models lacked this cache but gained performance benefits from instruction prefetching due to packing multiple instructions into each word.

The architecture featured eight eighteen-bit address registers (A0 through A7), eight eighteen-bit index registers (B0 through B7), and eight sixty-bit operand registers (X0 through X7). Most address registers corresponded directly with operand registers to facilitate efficient memory operations; A0 functioned as a scratch register.

Top-tier CPUs contained multiple functional units that allowed parallel execution of instructions. Expert assembly language programmers exploited this by interleaving independent instructions with memory fetches to hide slow memory latency, optimizing throughput via tight loops fitting entirely within instruction cache.

The peripheral processor subsystem employed a "barrel and slot" scheduling method: each PP had dedicated memory and registers but shared a single execution unit cycling through them sequentially, enabling rudimentary hardware multiprogramming. Each PP contained 4096 bytes of twelve-bit memory along with an eighteen-bit accumulator; PPs managed all I/O channels and accessed central memory but possessed limited arithmetic capability and did not execute user application code—their function was strictly I/O handling to offload work from central CPUs.

Lower-tier Cyber CPUs included a CMU featuring four specialized instructions optimized for text processing: moving short or long strings, comparing strings, and collated string comparison. These unique sixty-bit instructions operated on six-bit fields within central memory, enabling complex string manipulations in one instruction cycle. Higher-end CPUs omitted CMU support since hand-coded loops typically outperformed these instructions.

Cyber systems generally ran CDC’s NOS (Network Operating System). NOS version 1 received updates until approximately 1981; NOS version 2 debuted in early 1982 with final revisions extending through December 1997 supporting DtCyber systems along with minor bug fixes and Y2K compliance patches. Alternative operating systems included NOS/BE or its predecessor SCOPE, both providing time-sharing capabilities for batch processing and interactive use. The older Kronos OS remained operational until around mid-1975. Due to application dependencies on specific character sets, many installations preferred maintaining older OS versions or applying patches to newer releases rather than performing complete migrations for compatibility reasons.

Cyber 180 series

The Cyber 180 series originated in 1973 at the Advanced Systems Laboratory, a collaborative effort between CDC and NCR located in Escondido, California. Initially known as the Integrated Product Line (IPL) and sometimes referred to as Cyber 80 during its development phase, the initiative sought to replace the NCR 6150 and CDC Cyber 70 product lines by introducing a virtual memory architecture. As part of this effort, Software Writer's Language (SWL), a language similar to Pascal, was created to serve as the foundation for all software and the operating system, originally named IPLOS. SWL was subsequently renamed PASCAL-X before ultimately becoming Cybil. Following the dissolution of the joint venture in 1976, CDC assumed full responsibility for development and rebranded the system as Cyber 180. The first units were released in 1982, with the NOS/VE operating system being announced a year later in 1983.

With industry standards transitioning to an eight-bit byte structure, CDC introduced machines capable of running in both 60-bit and 64-bit modes. The 64-bit NOS/VE operating system leveraged virtual memory hardware, whereas older 60-bit systems continued to operate under NOS and NOS/BE in a compatibility mode.

Genuine Cyber 180 systems are microcoded processors designed to support both instruction sets concurrently, featuring hardware distinct from previous models. The smaller exchange package used for 170-mode operation was embedded within a larger package supporting 180-mode operation, utilizing a virtual machine identifier (VMID) to toggle between instruction sets.

The initial product range comprised three authentic Cyber 180 models: P1, P2, and P3. The P2 and P3 were larger water-cooled designs; the P2 was developed by a team in Mississauga, Ontario—the same group responsible for designing the more compact P1—while the P3 originated from Arden Hills, Minnesota. The P1 stood out as an innovative air-cooled system housed in a cabinet with sixty circuit boards and operated on standard 60 Hz electrical power without requiring motor-generator sets. Concurrently, a high-performance model designated 990 (codenamed THETA) was under development at Arden Hills.

Initially marketed under the designation 170/8xx without emphasizing their new dual 8/64-bit architecture, these systems ran a primary control program called Environmental Interface (EI) in 180 mode. The legacy NOS operating system for the 170 series utilized fixed large memory pages; subtle clues such as messages about "building page tables" and expanded deadstart panels hinted at the underlying new architecture.

Peripheral processors within true Cyber 180 systems are always 16-bit machines that determine their instruction set based on the sign bit. Single-word input/output instructions remain at 16 bits, facilitating configuration that allows EI to operate alongside NOS and existing software designed for 170-mode operation. To safeguard proprietary technology, CDC replaced its Deadstart Diagnostic Sequence source code with a proprietary Common Tests & Initialization package.

The original product offerings included models such as the 170/825 (P1), 170/835 (P2), and 170/855 (P3), along with enhanced versions like the 170/865 and 170/875. The release of the 825 experienced delays due to microcode modifications aimed at balancing its performance relative to the P2. The 865 and 875 were improved iterations of older models like the 170/760 but featured expanded memory capacities; notably, the 875 incorporated faster main processor memory derived from the Cyber 205 line.

After several years, CDC disclosed the full capabilities of these systems to customers and rebranded them as authentic Cyber 180 models: specifically, the 180/825 (P1), 180/835 (P2), and 180/855 (P3). The model range further expanded with the addition of the model 815 featuring delayed microcode execution, while faster microcode versions returned to model 825. The THETA project ultimately evolved into the high-end Cyber 990 system.

Cyber 200 series

In 1974, CDC launched the STAR, a pioneering 64-bit architecture that incorporated virtual memory and vector processing instructions tailored for intensive mathematical computations. Its vector pipeline could handle sequences up to 65,536 elements, but due to significant latency, optimal performance required extremely long vectors. To integrate the vector unit, the scalar processor was simplified, which resulted in slower operation relative to the CDC 7600. As a result, the STAR's commercial success was limited, with roughly three units sold.

During the late 1970s, CDC tackled these shortcomings by introducing the Cyber 203, a rebranding effort to move past the STAR's lackluster reception. This model featured an overhauled scalar processor and loosely coupled input/output systems while maintaining the original STAR vector pipeline. About two Cyber 203 machines were either delivered new or converted from STAR-100 units.

The Cyber 205, announced in 1980 as the Cyber 203's successor, saw its initial deployment at the UK Meteorological Office in 1981. This system replaced the STAR’s vector pipeline with newly engineered pipelines; both scalar and vector components utilized ECL gate array integrated circuits cooled by Freon. Configurations offered either two or four vector pipelines, with the four-pipeline variant theoretically capable of reaching 400 64-bit MFLOPs and 800 32-bit MFLOPs, though such peak rates were seldom attained outside of meticulously optimized assembly language. The instruction set employed was V-CISC, featuring specialized instructions for hardware-level searches, matrix operations, and cryptographic tasks.

In 1983, following the introduction of the Series 600 model—which differed primarily in memory technology and packaging—the original Cyber 205 was redesignated as Cyber 205 Series 400. Most deployments utilized two-pipeline configurations; only one known system featured four pipelines.

The Cyber 205 design served as a foundation for the ETA10 after its development team established ETA Systems in September 1983. The last version of this lineage, initially called Cyber 250 with a price tag of $20 million and planned for release in 1987, was later renamed ETA30 when ETA Systems reintegrated into CDC.

CDC CYBER 205

Architecture: ECL/LSI logic
- Cycle time: 20 ns (50 MHz)
Peak performance: up to 800 Mflops FP32 and 400 Mflops FP64
Memory options: 1, 2, 4, 8 or 16 million 64-bit words with bandwidths of either 25.6 or 51.2 Gbps
I/O capabilities: Eight ports each supporting up to sixteen channels at 200 Mbits per second

Cyberplus or Advanced Flexible Processor (AFP)

The Cyberplus—also known as the Advanced Flexible Processor (AFP)—is a 16-bit CPU that optionally supports 64-bit floating-point operations and comes equipped with either 256K or 512K words of 64-bit memory. It succeeded the Flexible Processor (FP), which had been developed in the early 1970s for processing radar and image data. The FP’s control unit included hardware enabling conditional execution of microinstructions based on nearly fifty different conditions.

By 1986, there were at least twenty-one multiprocessor Cyberplus installations operating with up to 256 processors each capable of delivering around 250 MFLOPS. These systems interfaced with existing Cyber models (170/835, 845, 855, and 180/990) through a direct memory interconnect architecture (MIA), supported by NOS version 2.2.

In terms of physical dimensions, each Cyberplus unit matched standard mainframe module sizes akin to those found in Cyber 180 systems and weighed approximately one ton depending on its floating-point unit configuration.

Included software packages

System software
FORTRAN cross compiler
MICA assembler
Load File Builder
ECHOS simulator
Debugging and dump utilities
Maintenance tools

Prominent users encompassed institutions such as the University of Georgia and Germany’s Gesellschaft für Trendanalysen (GfTA).

A fully equipped setup with all 256 processors could theoretically achieve a peak performance of around 64 GFLOPS while weighing close to 256 tons. A nine-unit configuration was capable of handling one megapixel image pair per second for comparative analysis and preprocessing functions.

Cyber 18

The Cyber 18, a 16-bit minicomputer succeeding the CDC 1700, was chiefly utilized in real-time operational settings. One of its principal roles was serving as the core for the 2550 communications processor employed by CDC 6000 series and Cyber 70/Cyber 170 mainframes. The 2550 was engineered by CDC's Communications Systems Division located in Santa Ana, California (STAOPS), which also developed the M1000 CP (subsequently renamed C1000) communication processor tailored for IBM mainframe networks, originally acquired from Marshall MDM Communications. This 2550 system integrated the Cyber 18 with an assembly of three circuit boards.

Supported programming languages encompassed Pascal, assembly language, FORTRAN, BASIC, and RPG II. Its operating environments included RTOS (Real-Time Operating System), MSOS 5 (Mass Storage Operating System), and TIMESHARE 3 (a time-sharing system).

The Cyber 18 family featured variants such as the Cyber 18-17, essentially a rebranded System 17 based on the 1784 processor architecture, along with models like the 18-05, 18-10, 18-20, and 18-30. These versions incorporated microprogrammable processors with memory capacities reaching up to 128K words, additional general-purpose registers, and expanded instruction sets; notably, the 18-30 model housed dual processors. A specialized 32-bit iteration named MP32 was created for the National Security Agency to assist in cryptanalysis, embedding Fortran mathematical runtime routines within its microcode. Although attempts were made by the Soviet Union to procure these systems, export restrictions imposed by the U.S. government prevented sales; components from the MP32 were subsequently reused in Cyber 18 manufacturing. Furthermore, the Cyber 18 played a role in monitoring operations of the Alaskan Pipeline.

Cyber 1000

Originally designated as M1000/C1000 and later renamed Cyber 1000, this system operated as a message store-and-forward platform for the Federal Reserve System. A variant without a hard drive found use within Bell Telephone. This RISC-based processor system evolved into the Cyber 1000-2, which introduced a Line Termination Sub-System incorporating 256 Zilog Z80 microprocessors. During the mid to late 1980s, Bell Operating Companies procured substantial quantities for data communications purposes.

Later iterations included the XN10 model, which featured an enhanced processor supporting direct memory access instructions and reduced its physical footprint from two cabinets to one. Following this, the XN20 further decreased size by integrating the Line Termination Sub-System onto a single card utilizing the improved Z180 microprocessor. The XN20 was in pre-production when CDC's Communication Systems Division ceased operations in 1992.

Jack Ralph held the position of chief architect for the Cyber 1000-2, XN10, and XN20 projects, while Dan Nay served as chief engineer specifically for the XN20.

External links

CDC IBM front end bows (Network World, December 1, 1986, p. 4)
Cyber documentation at bitsavers.org