ETA10
| Company type | Subsidiary |
|---|---|
| Industry | Supercomputing |
| Predecessor | Control Data Corporation (CDC) |
| Founded | 1983 |
| Defunct | 1989-04-17 |
| Fate | Shut down due to financial losses; reabsorbed into CDC |
| Headquarters | United States |
| Products | ETA10 vector supercomputer |
| Parent | Control Data Corporation (CDC) |
The ETA10 represents a vector supercomputer engineered and sold by ETA Systems, a subsidiary formed from Control Data Corporation (CDC). This machine is a direct descendant of the CDC Cyber 205, which itself was developed from the groundbreaking CDC STAR-100 vector supercomputer.
On April 18, 1983, CDC revealed the establishment of ETA Systems along with plans for a successor to the Cyber 205 at the Frontiers of Supercomputing conference held at Los Alamos National Laboratory. Initially designated as the Cyber 2XX and subsequently GF-10, the project was eventually renamed ETA10. Prototype units were operational by mid-1986, with initial shipments commencing in December of that year. The official market introduction occurred in April 1987 at an event hosted by its inaugural client, Florida State University's Scientific Computational Research Institute.
Although the ETA10 showcased significant technological progress, CDC decided to shut down ETA Systems on April 17, 1989, due to ongoing financial deficits, halting further production. Following this closure, numerous clients, including Florida State University, migrated to Cray supercomputers.
Historical development
CDC's prominence in supercomputing dates back to the CDC 6600. A notable figure, architect Seymour Cray, departed CDC after conflicts over the CDC 8600 project to establish Cray Research. Concurrently, CDC developed the CDC STAR-100 under Neil Lincoln’s leadership. The STAR-100 was outpaced by Cray Research’s successful Cray-1, prompting CDC to introduce the Cyber 203 and later the Cyber 205. The Cyber 205 achieved moderate market success competing against the Cray X-MP. In response to industry demands for faster development timelines, CDC adopted new approaches for creating the Cyber 205’s successor.
Following its separation from CDC in September 1983, ETA Systems aimed to deliver a supercomputer with a clock cycle below 10 nanoseconds. This ambition included novel techniques such as cooling CMOS processors with liquid nitrogen. The ETA10 fulfilled its initial target of delivering 10 GFLOPS, with some variants reaching approximately 7 ns (143 MHz), a remarkable feat during the mid-1980s. In total, ETA produced seven liquid nitrogen-cooled models alongside twenty-seven air-cooled units. The CMOS technology used generated considerably less heat compared to prior integrated circuits. Although a follow-up model called Cyber 250 or ETA30 (targeted at 30 GFLOPS) was planned for release in 1987, it never materialized. Eventually, ETA was reabsorbed into CDC and ceased operations on April 17, 1989.
Operating systems and applications
The ETA10 operated using either ETA’s proprietary EOS operating system—which attracted significant criticism—or a ported version of UNIX System V (Release 3) developed by Lachman Associates. While EOS presented numerous challenges, customers generally preferred the UNIX variant.
EOS maintained binary compatibility with CDC’s VSOS system designed for the Cyber 205, incorporating demand-paged virtual memory with dual page sizes optimized to leverage faster hardware pipelines. VSOS focused primarily on batch processing but suffered from limited adoption and feature stagnation due to its narrow user base.
To enhance user experience, EOS merged VSOS’s batch processing capabilities with UNIX features into a hybrid operating system supporting both batch jobs and interactive development via UNIX workstations.
The bulk of EOS was programmed in Cybil, a Pascal-like language created by Control Data for use in later Cyber systems. This replaced VSOS’s original implementation in IMPL, a Fortran-like language derived from LTSS origins. The command-line interface traced its heritage back to EXEC*8.
Though EOS debuted alongside early hardware releases, it encountered typical issues common to new operating systems at launch, leading some customers to delay payments. Subsequently, ETA introduced a UNIX port for the ETA-10 series that gained quicker acceptance among users despite initially supporting only single-processor kernels that did not fully exploit configurations with up to eight CPUs.
Criticism
Although the ETA10 eventually incorporated UNIX, its system software remained a significant weakness. The NSF evaluation panel noted software crashes occurring roughly every 30 hours and subpar multi-processor execution performance across all eight CPUs. While the hardware represented cutting-edge technology, the system as a whole was considered "highly underdeveloped."
Additional factors such as delayed deliveries, operational difficulties, and management challenges accelerated ETA's downfall. The Fortran compiler (ftn200) was outdated, maintaining proprietary extensions that impeded source code portability—a major drawback as the industry moved toward cross-platform compatibility. In terms of compiler optimization, ETA lagged behind competitors like Japanese supercomputer manufacturers and Cray Research.
During this period, hardware companies including CDC typically struggled with software development. CDC depended largely on externally created operating systems, such as those from Lawrence Livermore Laboratories, which restricted its software offerings and limited user adoption.
NASA reported that ETA hardware failed acceptance testing at the Ames Research Center, a critical event that resulted in NASA—and later the Department of Defense—rejecting the system. Within CDC, this rejection is widely regarded as the decisive factor that precipitated ETA's collapse.
Models
The ETA10 series comprised four distinct models, each available in either single- or multi-processor configurations.
The Models E and G were high-end systems cooled by liquid nitrogen. The Model E operated with a 10.5 ns clock cycle (~95 MHz) and supported up to eight processors, delivering peak performance of 8.32 GFLOPS. The Model G improved upon this with a 7 ns clock cycle (~142 MHz), achieving up to 10.3 GFLOPS using eight processors.
In contrast, the Models P and Q offered slower, more cost-effective air-cooled alternatives. The Model P, nicknamed "Piper," featured a 24 ns clock cycle, while the two-processor Model Q ran at 19 ns cycles.
Performance
The ETA10 lineup ranged from high-performance liquid-nitrogen cooled models (such as ETA10-E and G) to more economical air-cooled variants (ETA10-P and Q), covering a performance spectrum of approximately 27:1. The top-tier models reached peak computational speeds around 10 GFLOPS.
On the LINPACK benchmark for a 100 × 100 matrix, a single-processor ETA10 achieved 52 MFLOPS.
Description
The ETA10 was designed as a multiprocessor system capable of supporting up to eight CPUs, each architecturally similar to a dual-lane Cyber 205 CPU. A notable innovation was the CPU construction: utilizing 250 CMOS gate array integrated circuits mounted on a 44-layer printed circuit board (PCB). Each gate array contained about 20,000 gates fabricated with Honeywell’s VHSIC program technology at a 1.25-μm scale—much finer than the standard commercial processes of 3 to 5 μm at that time.
CMOS technology was selected due to its high gate density, which helped minimize both on-chip and off-chip delays. Timing delays within the CPU were controlled through precise PCB tuning combined with advanced logic design techniques, incorporating JTAG and BIST capabilities. The design process utilized a combination of internal simulators and one of the earliest commercial electronic design automation schematic capture tools provided by Mentor Graphics, replacing older text-based netlist methodologies.
Although CMOS operated slower than the bipolar emitter-coupled logic typically used in vector supercomputers, cooling CPUs with liquid nitrogen at -196.15 °C effectively doubled their performance compared to air cooling. However, this cryogenic cooling was not applied to local or shared memory components since it offered minimal advantages there. To facilitate this cooling method, ETA engineered a proprietary closed-loop system because no commercial options were available at the time. Additionally, manufacturing the complex 44-layer PCB required novel fabrication techniques developed specifically by ETA.
Each CPU contained 4 million words of local SRAM memory and interfaced with a shared memory pool of 256 million words constructed from DRAM modules. A communication buffer enabled synchronization between CPUs and supported multiprocessor protocols. Input/output operations were managed by between one and eighteen processors that accessed shared memory directly. Communication between CPUs and I/O devices was conducted via fiber-optic connections—a pioneering interconnect technology during the 1980s.
Installations
Prior to the reintegration of ETA Systems into CDC, a total of 25 ETA10 units were supplied to prominent organizations, including:
- Florida State University, which received the very first ETA10 (serial number 1) on January 5, 1987
- Johnson Space Center
- John von Neumann Center (JVNC), where unsold ETA10 machines were destroyed to avoid unauthorized use
- Purdue University, which contributed to the creation of ETA System V, a System V UNIX derivative tailored for the ETA10
- Tokyo Institute of Technology, delivered an 8-CPU liquid-cooled model in 1988
- Meiji University, which obtained an ETA10-P in 1989
- Academia Sinica
- Deutscher Wetterdienst
During the late 1980s, remaining ETA10 computers were donated to secondary schools through the SuperQuest computer science competition, with recipients such as:
See also
- EOS, the proprietary operating system developed by ETA Systems
- Cray Time Sharing System
- NLTSS
- Timeline of operating systems