Espresso (processor)
| Company type | Central processing unit |
|---|---|
| Industry | Semiconductor |
| Founded | 2011 |
| Founder | IBM, Nintendo |
| Headquarters | Japan, United States |
| Products | 32-bit PowerPC-based CPU for Wii U |
| Parent | IBM, Nintendo |
Espresso refers to the 32-bit central processing unit (CPU) utilized in Nintendo's Wii U gaming system. Engineered by IBM, this processor was fabricated employing a 45 nm silicon-on-insulator manufacturing technique. The Espresso CPU is housed together with an AMD Radeon-based GPU named "Latte" on a single MCM, which is produced by Renesas. This chip was first disclosed at the E3 2011 event and became available in November 2012.
Design
The Espresso processor, a PowerPC-based design with three cores integrated into one chip, was co-developed by IBM and Nintendo to balance performance with energy efficiency. Both the CPU and GPU are combined on a unified multi-chip module (MCM) substrate, which simplifies the overall architecture, accelerates data exchange, reduces power consumption, and cuts down on manufacturing costs and physical space requirements. Assembly of these MCMs took place in Japan under Renesas. IBM’s East Fishkill, New York facility handled the production of Espresso using 45 nm Silicon on Insulator (SOI) technology along with embedded DRAM (eDRAM) cache integration.
Although Nintendo has not officially confirmed specifics, investigations by hackers and hardware teardowns have shed light on Espresso’s designation, dimensions, and operating frequencies. Its microarchitecture is reminiscent of the earlier Broadway and Gekko processors—both based on PowerPC 750—but includes enhancements such as expanded cache sizes and support for multiprocessing.
Contrary to speculation, the Wii U’s CPU does not stem from IBM’s high-performance POWER7 server processor, which would have resulted in higher production expenses and a larger chip footprint. While Espresso shares certain features with POWER7—like eDRAM technology and similarities in instruction sets—these commonalities are primarily superficial rather than fundamental.
Specifications
- PowerPC cores capable of out-of-order execution
- Fabricated with 45 nanometer process technology
- Utilizes IBM’s silicon on insulator (SOI) fabrication method
- Maintains backward compatibility with Broadway and Gekko CPUs
The following details have been derived from reverse engineering efforts by hacker Hector Martin (marcan), as neither Nintendo nor IBM has officially released them:
- Core architecture based on Broadway design
- Three cores running at 1.243125 GHz each
- Symmetric multiprocessing enabled with MESI/MERSI cache coherence protocols
- Each core supports superscalar execution issuing up to 4 instructions per clock cycle
- Includes a 32-bit integer unit alongside a 64-bit floating-point unit (or alternatively two 32-bit SIMD units known as "paired singles")
- An unconventional total of 3 MB Level 2 cache distributed as follows: Core 0 houses 512 KB, Core 1 contains 2 MB, Core 2 holds 512 KB
- Pipeline depth of 4 stages for integer operations and 7 stages for floating-point calculations
- Six execution units per core, totaling eighteen across all cores
- Chip die measures approximately 27.73 mm² (dimensions: 4.74 mm × 5.85 mm)
