Gekko (processor)
| Company type | Microprocessor |
|---|---|
| Industry | Semiconductor |
| Founded | 2000 |
| Founder | IBM, Nintendo |
| Products | 32-bit superscalar, out-of-order PowerPC microprocessor |
| Parent | IBM |
Gekko is a 32-bit superscalar, out-of-order PowerPC microprocessor developed by IBM in 2000 specifically for Nintendo. It served as the CPU in Nintendo's sixth-generation console, the GameCube, and was subsequently utilized in the Triforce Arcade Board.
Development
The Gekko processor was engineered to efficiently manage various gaming tasks such as scripting, artificial intelligence, physics calculations, collision detection, custom lighting effects, geometry transformations, and rapid graphics data transfer.
In 1999, IBM and Nintendo finalized a significant agreement—IBM’s largest single CPU order at that time—to produce a processor operating near 400 MHz. IBM adapted their existing PowerPC 750CXe chip to align with Nintendo’s specifications by enhancing the bus architecture, optimizing Direct Memory Access (DMA), compression techniques, and refining the floating-point unit with specialized SIMD instructions. These improvements facilitated sophisticated lighting and geometric computations while enabling compressed data bursts to be sent directly to the GPU.
Gekko acted as the foundational design for IBM’s subsequent Broadway CPU, which powered the Wii system.
Features
- Modified core based on the PowerPC 750CXe
- Operating frequency: 486 MHz
- Supports superscalar out-of-order instruction execution
- Equipped with two 32-bit integer ALUs featuring four pipeline stages
- Includes a 64-bit double-precision floating-point unit (7 pipeline stages) with paired singles SIMD support delivering up to 1.9 GFLOPS
- Contains Branch Prediction Unit (BPU) and Branch Target Instruction Cache (BTIC)
- Features Load-Store Unit (LSU), System Register Unit (SRU), and Memory Management Unit (MMU)
- Implements approximately 50 new SIMD instructions optimized for three-dimensional graphics processing
- Utilizes a 64-bit enhanced 60x front-side bus running at 162 MHz, providing peak bandwidth of 1.3 GB/s to GPU and chipset
- On-chip memory includes 64 KB L1 cache (split evenly between instruction and data caches) and a 256 KB L2 cache
- Achieves performance of 1125 DMIPS according to Dhrystone 2.1 benchmark
- Fabricated using IBM’s 180 nm six-layer copper wiring process; die measures 43 mm²
- Power specifications: 1.8 V logic/I/O voltage with power dissipation of 4.9 W
- Packaged in a 27 × 27 mm PBGA containing 256 pins
- Comprises approximately 6.35 million logic transistors within a total of 18.6 million transistors
See also
- Broadway (microprocessor), the CPU used in the Wii console
- MIPS R4300, the processor found in the Nintendo 64