Alpha 21064A

Digital Equipment Corporation

Company type	Public
Industry	Computer hardware
Founded	November 8, 1957 (1957-11-08) in Maynard, Massachusetts, United States
Founder	Ken Olsen, Harlan Anderson
Defunct	February 26, 1998 (1998-02-26)
Fate	Acquired by Compaq
Headquarters	Maynard, Massachusetts , United States
Products	Alpha 21064 microprocessor, among others

The Alpha 21064 is a microprocessor created and produced by Digital Equipment Corporation, implementing the Alpha (initially known as Alpha AXP) instruction set architecture (ISA). Originally designated as the DECchip 21064 prior to its rebranding in 1994, it carried the code name EV4. Introduced in February 1992 with mass production commencing by September, this was Digital's inaugural commercial microprocessor based on the Alpha ISA. The Alpha 21064 was later succeeded by the Alpha 21064A in October 1993, which itself was replaced by the Alpha 21164 in 1995.

History

The first Alpha processor was a prototype chip called EV3, manufactured using Digital’s 1.0-micrometre CMOS-3 technology. This initial version lacked a floating point unit and featured only 1 KB caches, serving primarily to validate advanced circuit design methods and facilitate firmware and operating system development.

The production-ready chip, EV4, utilized Digital's 0.75 μm CMOS-4 fabrication process. The design team was led by micro-architects Dirk Meyer and Edward McLellan—Ed concentrated on the issue logic while Dirk oversaw other critical components—while Jim Montanaro directed circuit implementation. The EV3 powered the Alpha Demonstration Unit (ADU), a multiprocessor platform employed to develop software for the Alpha ecosystem prior to EV4’s release.

Revealed at the 39th International Solid-State Circuits Conference in February 1992, the initial 150 MHz sample was priced at $3,375 per unit for orders exceeding 100 pieces, with volume shipments beginning in September of that year. Subsequent price cuts followed: by early 1993, the cost of the 150 MHz variant had fallen to $1,096 per unit for quantities over 1,000. A faster 200 MHz version was introduced in February 1993, with sample pricing at $3,495 and volume pricing of $1,231 for orders above 10,000 units; shipments started in August.

With the launch of new models—the Alpha 21066 and 21068 in September 1993—Digital adjusted its strategy on existing 21064 processors and introduced a 166 MHz variant priced at $499 per unit for orders beyond 5,000 units. Pricing modifications persisted into mid-1994 to maintain competitiveness against processors such as Intel's Pentium.

Digital Equipment Corporation was the exclusive manufacturer of the Alpha 21064, producing it at facilities located in Hudson, Massachusetts and South Queensferry, Scotland.

Users

The primary applications for the 21064 were in high-performance workstations and server platforms. Key adopters included:

• Aspen Systems deploying it within Alpine workstations
• Carrera Computers utilizing it in Hercules 150, Hercules 200, and Pantera II workstation models
• Cray Research, which incorporated the 150 MHz version into Cray T3D supercomputer systems
• Digital itself integrating the processor into various systems: entry-level DECpc AXP 150 workstations, entry-level servers (DEC 2000 AXP), workstations and servers (DEC 3000 AXP), mid-range servers (DEC 4000 AXP), as well as high-end servers (DEC 7000/10000 AXP)
• Encore Computer, employing it within Infinity R/T high-end real-time computing systems

Performance

From its launch until 1993, the Alpha 21064 held the title of highest-performing microprocessor until IBM introduced its multi-chip POWER2. It continued to be the fastest single-chip microprocessor until October 1993 when the faster, 275 MHz Alpha 21064A was released.

Description

The Alpha 21064 is a superpipelined, dual-issue superscalar processor that executes instructions in program order. It can dispatch up to two instructions per cycle through four distinct functional units: integer, floating-point (FPU), address, and branch units. The integer pipeline consists of seven stages, while the floating-point pipeline extends to ten stages. The initial four stages are common to both pipelines and are controlled by the I-box.

I-box

Serving as the control unit, the I-box is responsible for fetching, decoding, issuing instructions, and overseeing pipeline operations. During the first stage, it retrieves two instructions from the instruction cache (I-cache). Branch prediction is performed in the second stage using either static or dynamic techniques: static prediction evaluates the sign bit of branch displacement to assume backward branches are taken; dynamic prediction relies on a 2,048-entry, single-bit branch history table with an accuracy near 80%. The penalty for incorrect branch prediction is four cycles.

Instruction decoding takes place in stage three. In stage four, the I-box checks resource availability to issue paired instructions. Allowed instruction pairs include integer operate paired with floating-point operate, load/store combined with operate instructions, integer operate with integer branch, or floating-point operate alongside floating-point branch. Pairs such as integer operate with floating-point store or floating-point operate with integer store are prohibited. If pairing is unsuccessful or resources are limited, the first four pipeline stages stall until issuance becomes feasible.

The I-box incorporates two fully associative instruction translation buffers (ITBs) for virtual-to-physical address translation: an eight-entry ITB catering to 8 KB pages and a four-entry ITB for 4 MB pages. Both buffers utilize a not-last-used replacement policy.

Execution

Instruction execution begins at stage five for all instructions, with register file reads occurring in stage four. Pipelines that start at stage five cannot be stalled.

Integer unit

The integer unit executes all integer instructions and includes both the integer register file (IRF) and the E-box. The IRF contains thirty-two 64-bit registers equipped with four read ports and two write ports shared between the integer and branch units. The E-box houses an adder, logic unit, barrel shifter, and multiplier. Most integer instructions complete at stage five with a one-cycle latency; however, multiply, shift, and byte manipulation instructions require additional cycles. Although the barrel shifter is pipelined, shift and byte operations complete by stage six with a two-cycle latency. To conserve die area, the multiplier is not pipelined, resulting in multiply latencies ranging from 19 to 23 cycles depending on operand values. Integer results are written back to the IRF at stage seven.

Address unit

The address unit ("A-box") manages load and store instructions. Operating concurrently with the integer unit, it uses its own displacement adder for virtual address calculation instead of relying on the integer unit’s adder. A 32-entry fully associative translation lookaside buffer (TLB), named the data translation buffer (DTB), performs virtual-to-physical address translation. The 21064 supports a virtual address space of 43 bits (8 TB) and a physical address space of 34 bits (16 GB).

Store operations utilize a 4-entry by 32-byte write buffer that merges adjacent stores and postpones writes to minimize system bus traffic, thereby enhancing load performance.

Floating-point unit

The floating-point unit (FPU) incorporates a floating-point register file (FRF) consisting of thirty-two 64-bit registers, equipped with three read ports and two write ports. Additionally, it includes the F-box, which houses a floating-point pipeline alongside a non-pipelined divider that processes one bit per cycle.

During the fourth pipeline stage, the FRF is accessed to read data, which is then decomposed into fraction, exponent, and sign components. For addition operations, calculations for exponent difference and normalization prediction commence; for multiplication, a tripled multiplicand (3 × multiplicand) is generated.

Stages five and six handle alignment or normalization shifts as well as sticky-bit computations for addition and subtraction. Multiplication employs a pipelined, two-way interleaved radix-8 Booth algorithm array. The final addition and rounding steps take place in stage eight. Results from floating-point operations are written back to the FRF in stage ten.

Floating-point instructions exhibit a pipeline latency of six cycles. Division operations in single-precision and double-precision formats are executed by the non-pipelined divider with latencies of 31 cycles and 61 cycles respectively.

Caches

The 21064 processor integrates two primary on-chip caches: an 8 KB data cache (D-cache) utilizing a write-through strategy and an 8 KB instruction cache (I-cache). Both caches are direct-mapped to enable single-cycle access with 32-byte cache lines. They are constructed from six-transistor SRAM cells occupying an area of 98 μm² each. The cache arrays measure 1,024 cells in width by 66 cells in height, with the uppermost two rows reserved for redundancy purposes.

An optional external secondary cache, known as the B-cache, supports sizes ranging from 128 KB up to 16 MB. It operates at frequencies between one-third and one-sixteenth of the internal clock speed (equivalent to 12.5 to 66.67 MHz when the internal clock runs at 200 MHz). The B-cache is direct-mapped with a default cache line size of 128 bytes and is accessed through the system bus.

External interface

The external interface features a 128-bit wide data bus operating at speeds from half to one-eighth of the internal clock frequency (25 to 100 MHz when the internal clock is 200 MHz). The bus width is configurable, allowing certain systems to utilize a narrower 64-bit interface. Additionally, it includes a 34-bit address bus.

Fabrication

The Alpha 21064 chip contains approximately 1.68 million transistors and was manufactured using Digital’s CMOS-4 fabrication process with a feature size of 0.75 μm and three layers of aluminum interconnect. The initial EV4 die measures 13.9 mm by 16.8 mm, totaling an area of 233.52 mm². A subsequent revision, the EV4S, employed CMOS-4S technology—a process featuring a 10% optical shrink reducing feature size to 0.675 μm—and measured 12.4 mm by 15.0 mm (186 mm²).

Operating at a voltage supply of 3.3 volts, the EV4 dissipated up to 30 watts when running at 200 MHz. The EV4S variant lowered power consumption to a maximum of 21 watts at 150 MHz, increasing to 27 watts at its peak frequency of 200 MHz.

Package

This processor is enclosed within a pin grid array (PGA) package made from alumina ceramic, measuring approximately 61.72 mm on each side with a total of 431 pins. Out of these pins, 291 are dedicated to signal transmission while the remaining 140 provide power and ground connections. The heatsink attaches directly to the package via nuts secured on two studs linked to a tungsten heat spreader.

Alpha 21064A

The Alpha 21064A, also known as the DECchip 21064A and internally referred to as EV45, represents an improved iteration of the original Alpha 21064 introduced in October 1993. It was available at clock frequencies including 200, 225, 233, 275, and 300 MHz. The model running at 233 MHz was released on July 6, 1994, priced at US$788 per unit for orders of 5,000 units; this version replaced the earlier 225 MHz model while offering a price reduction of approximately ten percent. Simultaneously, the price for the 275 MHz variant dropped by twenty-five percent to US$1,083 per unit. The fastest model at 300 MHz was announced in October 1995 and became available by December that year. A specialized version labeled as the 21064A-275-PC was limited for use with Windows NT or compatible operating systems.

Positioned as Digital’s flagship microprocessor, the Alpha 21064A found widespread adoption in high-end systems such as Digital’s DEC 3000 AXP, DEC 4000 AXP, and DECset7000/10000 AXP series. Additional users included Aspen Systems with their Alpine workstation; BTG’s Action AXP275 RISC PC; Carrera Computers’ Cobra AXP275 workstation; NekoTech’s overclocked Mach2-289-T workstation; and Network Appliance’s NetApp storage solutions.

Architectural enhancements over its predecessor involved doubling primary cache capacities from eight kilobytes to sixteen kilobytes while adding parity protection for both cache tags and data arrays. Floating-point division latency was improved through an upgraded divider capable of retiring two bits per cycle on average. Furthermore, branch prediction was enhanced by implementing a larger branch history table containing four thousand ninety-six entries with two-bit saturating counters.

This chip comprises approximately 2.8 million transistors within a die measuring roughly fourteen point five millimeters by ten point five millimeters (152.25 mm²). It was fabricated using Digital’s fifth-generation CMOS-5 process technology featuring a half-micron (0.5 μm) feature size and four layers of aluminum interconnects.

Alpha 21066

The Alpha 21066, also referred to as the DECchip 21066 and carrying the codename LCA4 (Low Cost Alpha), represents a budget-friendly iteration of the Alpha 21064. Initial samples emerged in September 1993, with mass production commencing in early 1994. The first version operated at 166 MHz and was priced at US$385 per unit for orders of 5,000 units. A slower 100 MHz variant aimed at embedded applications began sampling in late 1994, with volume deliveries starting by the third quarter of 1995. It was notably the pioneering microprocessor to incorporate a PCI controller on-chip.

Targeted primarily for economical solutions—particularly Windows NT-based personal computers—the Alpha 21066 was utilized in Digital’s Multia client systems, AXPpci33 OEM motherboards, and AXPvme single-board computers. External manufacturers adopting this processor included Aspen Systems with their Alpine workstation, Carrera Computers’ Pantera I workstation, NekoTech’s Mach1-166 PC, and Parsys’ TransAlpha TA9000 supercomputer line.

Taking advantage of process miniaturization, this chip integrated components crucial for embedded markets: an on-die B-cache and memory controller supporting ECC, a modest graphics accelerator capable of handling up to 8 MB of VRAM for framebuffer tasks, a PCI controller, and a PLL clock generator designed to scale from a 33 MHz external clock signal.

Memory configurations supported B-cache sizes ranging from 64 KB to 2 MB and main memory capacities between 2 MB and 512 MB. The ECC mechanism could detect multiple-bit faults while correcting single-bit errors. To minimize manufacturing expenses, the system bus width was confined to 64 bits, reducing pin count and package dimensions but resulting in approximately a 20% decrease in bandwidth and overall performance—a compromise deemed acceptable for its intended applications.

This microprocessor housed about 1.75 million transistors on a die measuring 209.1 mm² (17.0 x 12.3 mm), produced using the CMOS-4S fabrication process at a 0.675 μm scale with three metal interconnect layers. It was enclosed within a sizable 287-pin CPGA package measuring roughly 57.4 x 57.4 mm.

Alpha 21066A

The Alpha 21066A, known by its codename LCA45, is an economical derivative of the Alpha 21064A, officially introduced on November 14, 1994. Models running at 100 and 233 MHz were shipped by March of the following year. Pricing stood at $175 for the lower frequency and $360 for the higher frequency (based on orders of 5,000 units), with a later addition of a 266 MHz variant.

Mitsubishi Electric provided second-source manufacturing for the 21066A under the designation M36066A, marking their initial production of Alpha microprocessors. Revealed concurrently with Digital's versions, Mitsubishi planned engineering sample availability in December 1994 and full-scale shipments by September 1995, pricing the 233 MHz chip at $490 per thousand units.

Differing from the Alpha 21064A, this version omitted the separate 16 KB instruction and data caches but included software-controllable power management features. Digital incorporated several variants of the 21066A into products that previously employed the original 21066, while Tadpole Technology utilized the 233 MHz model in its ALPHAbook 1 laptop.

The chip contained approximately 1.8 million transistors on a die sized at 161.32 mm², manufactured using Digital's CMOS-5 process at a feature size of 0.5 μm with three metal layers for interconnects; Mitsubishi employed a comparable fabrication method for their M36066A.

Alpha 21068

The Alpha 21068 (also known as DECchip 21068) was designed for embedded applications, closely resembling the 21066 but operating at a reduced clock frequency to lower both power consumption and manufacturing costs. Launched in September 1993 with mass production beginning in early 1994, this processor ran at 66 MHz and had a peak power dissipation of 9 W. Its initial price was set at $221 per unit for orders of 5,000, but Digital reduced this by 16% to $186 in July 1994.

Digital incorporated the Alpha 21068 into its AXPpci 33 motherboards as well as AXPvme single-board computers.

Alpha 21068A

The Alpha 21068A (DECchip 21068A) is a variant tailored for embedded systems, derived from the Alpha 21066A and operating at a clock speed of 100 MHz.

Chipsets

The earliest Alpha processors (21064 and 21064A) did not include standard chipset solutions, instead depending on proprietary ASICs developed by Digital for system interfacing. This approach increased costs for third-party developers. To mitigate these challenges, Digital introduced the DECchip 21070, known as "Apecs," a chipset aimed at original equipment manufacturers.

This chipset came in two versions: the DECchip 21071 intended for workstation use and the DECchip 21072 designed for high-performance workstations or entry-level uniprocessor servers. The primary distinctions between these were the width of the memory bus and supported memory capacity—the 21071 featured a 64-bit memory bus accommodating between 8 MB and 2 GB of parity-protected memory, whereas the 21072 offered a wider 128-bit bus supporting up to 4 GB of ECC-protected memory.

The chipset consisted of three components: the COMANCHE B-cache/memory controller, one or more DECADE data slice chips, and the EPIC PCI controller. DECADE chips managed data in 32-bit segments—two slices for the 21071 and four for the 21072—with EPIC providing PCI interface functionality.

Announced on January 10, 1994, with samples available shortly thereafter and volume shipments scheduled for mid-year, pricing was established at $90 for the 21071 and $120 for the 21072 when purchased in quantities of 5,000 units.

Notable users included Carrera Computers with their Pantera workstation line, as well as Digital itself employing these chipsets in select AlphaStation models and uniprocessor AlphaServer configurations.

References

• Alpha 21064 and 21064A Microprocessors Hardware Reference Manual, June 1996. Order number: EC-Q92UC-TE. Digital Equipment Corporation.
• Apiki, Steve; Grehan, Rick (March 1995). "Fastest NT Workstations". Byte.
• Bhandarkar, Dileep. "Alpha Implementations", IEEE Computer Society Technical Committee on Computer Architecture Newsletter, December 1995.
• Computergram International (25 February 1992). "DEC Reveals More On Alpha, Challenges Hewlett-Packard's Precision Architecture RISC". Computer Business Review.
• Computergram International (26 February 1992). "DEC Describes Its Alpha RISC, Kubota Discloses Its Plans". Computer Business Review.
• Computergram International (7 June 1994). "DEC slashes Alpha AXP Chip Prices by up to 31%". Computer Business Review.
• Computergram International (13 September 1993). "DEC adds Alphas for Personal Computers, Control". Computer Business Review.
• Computergram International (11 January 1994). "Microprocessor Report's Annual Chip Awards Declare Motorola 88110 the Part least likely to...". Computer Business Review.
• Computergram International (11 November 1994). "Mitsubishi Electric Is Ready To Sample Its First Alpha At Last". Computer Business Review.
• Computergram International (25 November 1994). "Mitsubishi's First Alpha Provides The Same Functionality As DEC's 21066A". Computer Business Review.
• Digital Equipment Corporation (10 January 1994). "Digital Introduces PCI-Based System Logic Chipsets For Alpha AXP 21064 Microprocessors And Announces The Industry's First PCI To PCI Bridge Chip". Press release.
• Dobberpuhl, Daniel W., Witek, Richard T. et al. "A 200-MHz 64-bit Dual-issue CMOS Microprocessor", Digital Technical Journal, Volume 4, Number 4, Special Issue 1992, pp. 35–50.
• Gwennap, Linley (12 September 1994). "Digital Leads the Pack with 21164", Microprocessor Report, Volume 8, Number 12.
• Krause, Reinhardt (13 September 1993). "DEC unveils two Alphas in PCI, embedded drive". Electronic News.
• Krause, Reinhardt (18 October 1993). "DEC readies 225/275MHz Alphas". Electronic News.
• Krause, Reinhardt (21 November 1994). "Alpha partners roll 233MHz 21066A". Electronic News.
• McKinney, Dina L. et al. "Digital's DECchip 21066: The First Cost-focused Alpha AXP Chip". Digital Technical Journal, Volume 6, Number 1, Winter 1994, pp. 66–77.
• McLellan, Edward (June 1993). "The Alpha AXP Architecture and 21064 Processor". IEEE Micro. pp. 36–47.
• Ryan, Bob; Thompson, Tom (January 1994). "RISC Grows Up". Byte.

Further reading

• "DEC Ventures into Microprocessor Market with Alpha". (4 March 1992). Microprocessor Report, Volume 6, Number 3.
• "Introduction of DEC's Alpha Architecture". (4 March 1992). Microprocessor Report, Volume 6, Number 3.
• "Digital Announces Extensive Alpha Processor Lineup". (18 November 1992). Microprocessor Report, Volume 6, Number 3.
• "Digital Unveils PCI Chipsets for Alpha Processors". (12 July 1993). Microprocessor Report, Volume 7, Number 9.
• "Alpha Expands to Entry-Level with Digital's 21066". (13 September 1993). Microprocessor Report, Volume 7, Number 12.
• Bhandarkar, Dileep P. (1995). Alpha Architecture and Implementations. Digital Press.
• Fox, Thomas F. (1994). "Designing High-Performance Microprocessors at Digital". Proceedings of the 31st Annual ACM-IEEE Design Automation Conference. pp. 586–591.
• Gronowski, Paul E. et al. (May 1998). "Design Techniques for High-Performance Microprocessors". IEEE Journal of Solid-State Circuits 33 (5): pp. 676–686.