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Alpha 21068

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Adapted from the English Wikipedia article Alpha 21068, available under CC BY-SA 4.0Updated 8 August 2025
Digital Equipment Corporation
IndustryComputer hardware
FoundedNovember 8, 1957; 69 years ago (1957-11-08)
Headquarters
Maynard, Massachusetts
,
United States
ProductsMicroprocessors, Computers

The Alpha 21064 is a microprocessor created and manufactured by Digital Equipment Corporation that implements the Alpha (initially known as Alpha AXP) instruction set architecture (ISA). Originally launched as the DECchip 21064 before being renamed in 1994, it carried the code name EV4. Announced in February 1992 and reaching mass availability by September of the same year, it marked Digital's inaugural commercial implementation of the Alpha ISA and microprocessor. The 21064A followed in October 1993, with the Alpha 21164 arriving in 1995.

History

The first Alpha prototype, called EV3, was produced using Digital's 1.0-micrometre CMOS-3 fabrication process. This early chip omitted a floating point unit and contained only 1 KB of cache memory, serving to validate advanced circuit design methods while facilitating initial firmware and operating system development.

The production-ready processor, EV4, was manufactured on Digital's 0.75 μm CMOS-4 process. Design leadership was provided by micro-architects Dirk Meyer and Edward McLellan, with Jim Montanaro responsible for circuit implementation. The EV3 powered the Alpha Demonstration Unit (ADU), a multiprocessor platform used for software development ahead of the EV4’s release.

Introduced at the 39th International Solid-State Circuits Conference in February 1992, a 150 MHz sample was priced at $3,375 for orders over 100 units, decreasing to $1,560 for quantities exceeding 1,000 units. Volume production began in September 1992.

By February 1993, pricing for the 150 MHz model dropped to $1,096 per unit for orders above 1,000 units. On February 25th, a 200 MHz variant was launched at $3,495 per sample kit and $1,231 per unit for bulk orders beyond 10,000 units, with shipments starting in August. By July, the cost of the 150 MHz version further declined to $853 per unit for orders over 10,000.

Following the September 1993 introduction of the Alpha 21066 and 21068 models, Digital adjusted its product lineup by releasing a new 166 MHz version priced at $499 for orders exceeding 5,000 units, while reducing the price of the 150 MHz model to $455.

On June 6, 1994, additional price reductions occurred: the 200 MHz model fell by 31% to $544 and the 166 MHz by 19% to $404 per unit for orders over 5,000 units, effective from July.

Digital Equipment Corporation remained the exclusive manufacturer without any secondary sourcing agreements. Production of the Alpha 21064 took place at Digital’s plants located in Hudson, Massachusetts and South Queensferry, Scotland.

Users

The primary applications of the 21064 were in high-performance workstations and server systems. Key adopters included:

  • Aspen Systems utilizing it in their Alpine workstation series
  • Carrera Computers employing it within Hercules 150, Hercules 200, and Pantera II workstations
  • Cray Research, which incorporated the 150 MHz variant in Cray T3D supercomputers
  • Digital Equipment Corporation (DEC), deploying it across a range from entry-level to premium systems such as DECpc AXP 150, DEC 2000 AXP, DEC 3000 AXP, DEC 4000 AXP, and DEC 7000/10000 AXP
  • Encore Computer, integrating it into their Infinity R/T high-end real-time computing platforms

Performance

At its launch, the Alpha 21064 held the position as the highest-performing microprocessor until IBM introduced its multi-chip POWER2 in 1993. It sustained its status as the fastest single-chip microprocessor until October 1993 when succeeded by the faster 275 MHz Alpha 21064A.

Description

The Alpha 21064 is a dual-issue superscalar microprocessor featuring a superpipelined architecture that executes instructions sequentially. It can dispatch as many as two instructions per clock cycle through four distinct functional units: integer, floating-point (FPU), address, and branch units. The integer pipeline consists of seven stages, while the floating-point pipeline extends to ten stages. The initial four stages for both pipelines are identical and controlled by the I-box.

I-box

Serving as the control center, the I-box manages instruction fetching, decoding, issuing, and pipeline coordination. During the first stage, two instructions are retrieved from the instruction cache (I-cache). Branch prediction takes place in the second stage using either static or dynamic techniques: static prediction presumes backward branches are taken based on the sign bit, whereas dynamic prediction relies on a 2,048-entry, 1-bit branch history table achieving roughly 80% accuracy. A mispredicted branch incurs a penalty of four cycles.

Instruction decoding occurs in stage three. In stage four, the I-box verifies resource availability to issue paired instructions. Instruction pairing depends on the integer register file ports and allows combinations such as integer operate with floating-point operate or load/store with operate instructions. However, two specific pairs are prohibited: integer operate with floating-point store and floating-point operate with integer store. If pairing is unfeasible or resources are constrained, the pipeline experiences a stall.

The I-box also contains two fully associative instruction translation buffers (ITBs) for virtual-to-physical address translation: one eight-entry ITB for 8 KB pages and another four-entry ITB for 4 MB pages. Both employ a not-last used replacement strategy.

Execution

Execution begins at stage five for all instructions, with register file reads occurring in stage four. Pipelines starting at stage five proceed without stalling.

Integer unit

The integer unit processes integer instructions and comprises the integer register file (IRF) alongside the E-box. The IRF includes thirty-two 64-bit registers equipped with four read ports and two write ports shared by both integer and branch units. The E-box integrates an adder, logic unit, barrel shifter, and multiplier. Most integer instructions complete at stage five with a one-cycle latency, except for multiply, shift, and byte manipulation operations. Due to pipelining constraints, shift and byte operations have a two-cycle latency. The multiplier is not pipelined to conserve die area, resulting in variable latency between 19 and 23 cycles for multiplication. Results are written back to the IRF during stage seven.

Address unit

The address unit ("A-box") is responsible for executing load and store instructions and includes its own displacement adder to compute virtual addresses independently of the integer unit, allowing parallel operation. It utilizes a 32-entry fully associative translation lookaside buffer (TLB), called the data translation buffer (DTB), which converts 43-bit virtual addresses into 34-bit physical addresses—supporting up to 8 terabytes of virtual memory and 16 gigabytes of physical memory.

For store operations, a 4-entry by 32-byte write buffer is employed that coalesces adjacent stores and defers writes, thereby reducing system bus traffic and enhancing load instruction performance.

Floating-point unit

The floating-point unit incorporates a register file (FRF) comprising thirty-two 64-bit registers, equipped with three read ports and two write ports, alongside the F-box, which houses a floating-point pipeline and a separate non-pipelined division unit.

During the fourth pipeline stage, the data is segmented into fraction, exponent, and sign components. Addition instructions initiate calculations for exponent differences and normalization predictions, while multiplication instructions produce a 3× multiplicand. The fifth and sixth stages handle alignment or normalization shifts and compute sticky bits for addition and subtraction operations. Multiplication employs a pipelined, two-way interleaved radix-8 Booth algorithm array. Final addition and rounding take place at stage eight, with results committed to registers by stage ten.

The floating-point pipeline exhibits a latency of six cycles; division operations in single-precision and double-precision formats are executed within the non-pipelined divide unit, incurring latencies of 31 and 61 cycles respectively.

Caches

The 21064 integrates two on-chip primary caches: an 8 KB data cache (D-cache) utilizing a write-through strategy and an 8 KB instruction cache (I-cache). Both caches are direct-mapped to enable single-cycle access and feature 32-byte line sizes. Constructed from six-transistor SRAM cells each occupying 98 μm2, the cache arrays measure 1,024 cells in width by 66 cells in height, with the uppermost two rows reserved for redundancy purposes.

An optional external secondary cache (B-cache) supports capacities ranging from 128 KB up to 16 MB. It operates at frequencies between one-third and one-sixteenth of the internal clock speed (12.5 to 66.67 MHz when the internal clock is at 200 MHz), employs direct mapping with a default line size of 128 bytes, and interfaces through the system bus.

External interface

The external interface features a configurable 128-bit data bus functioning at speeds from one-half down to one-eighth of the internal clock frequency (25 to 100 MHz at an internal clock of 200 MHz). Certain implementations utilize a 64-bit external interface variant. The address bus spans 34 bits in width.

Fabrication

Containing approximately 1.68 million transistors, the 21064 was manufactured using Digital’s CMOS-4 process technology with a 0.75 μm feature size and three layers of aluminum interconnects. The original EV4 die measures 13.9 mm by 16.8 mm (totaling 233.52 mm2). The EV4S version employs CMOS-4S technology—a 10% optical shrink featuring a reduced 0.675 μm feature size—with die dimensions of 12.4 mm by 15.0 mm (186 mm2).

Operating on a 3.3-volt power supply, the EV4 dissipates up to 30 watts at a frequency of 200 MHz, whereas the EV4S variant lowers power consumption to approximately 27 watts at the same clock rate.

Package

The processor is enclosed within a 431-pin alumina-ceramic pin grid array (PGA) package measuring 61.72 mm on each side. Of these pins, 291 are dedicated to signal transmission while the remaining 140 provide power and ground connections. A heatsink is mounted directly onto the package using nuts secured on studs that extend from a tungsten heat spreader.

Alpha 21064A

Introduced in October 1993 as the DECchip 21064A and internally referred to as EV45, the Alpha 21064A represents an upgraded iteration of the original Alpha 21064 processor. It was available at clock frequencies including 200, 225, 233, 275, and 300 MHz. On July 6, 1994, the earlier 225 MHz model was superseded by a faster 233 MHz variant priced at US$788 per unit in orders of at least 5,000 units—marking a price reduction of approximately ten percent compared to its predecessor. Concurrently, the price of the 275 MHz version was lowered by twenty-five percent to US$1,083 per unit under similar volume conditions. The highest-frequency model running at 300 MHz was announced in October of 1995 and shipped by December that year. A specialized version designated as the 21064A-275-PC was designed exclusively for use with Windows NT or compatible operating systems.

As Digital’s flagship Alpha microprocessor, the 21064A powered several high-performance systems including Digital’s DEC 3000 AXP, DEC 4000 AXP, and DEC 7000/10000 AXP series; Aspen Systems’ Alpine workstation; BTG’s Action AXP275 RISC PC; Carrera Computers’ Cobra AXP275 workstation; NekoTech’s Mach 2-289-T workstation—overclocked up to 289 MHz—and Network Appliance’s storage solutions.

Architectural enhancements featured in this model included doubling primary cache capacity from eight kilobytes to sixteen kilobytes with added parity protection; improved floating-point division latency achieved by an upgraded divider capable of retiring two bits per cycle on average; as well as an expanded branch history table containing four thousand ninety-six entries using two-bit prediction for more accurate branch prediction.

The chip contains approximately 2.8 million transistors within a die measuring roughly 14.5 mm by 10.5 mm (152.25 mm2), fabricated using Digital’s fifth-generation CMOS-5 process technology (0.5 μm node) incorporating four layers of aluminum interconnects.

Alpha 21066

The Alpha 21066, also known as the DECchip 21066 and internally referred to as LCA4 (Low Cost Alpha), represents a budget-friendly adaptation of the Alpha 21064. Initial samples were distributed starting in September 1993, with mass production commencing in early 1994. The first model operated at 166 MHz and was priced at US$385 per unit when purchased in batches of 5,000. A slower 100 MHz variant, aimed primarily at embedded applications, was sampled late in 1994 and released by mid-1995. This processor was notable for being the first to incorporate a PCI controller on the chip.

Targeted towards cost-sensitive markets—particularly personal computers running Windows NT—the Alpha 21066 was featured in Digital’s Multia client systems, AXPpci 33 OEM motherboards, and AXPvme single-board computers. Additional implementations included Aspen Systems’ Alpine workstation, Carrera Computers’ Pantera I workstation, NekoTech’s Mach 1-166 PC, and Parsys’ TransAlpha TA9000 series of supercomputers.

Thanks to process miniaturization, the chip integrated an on-die B-cache and a memory controller with ECC capabilities, alongside a basic graphics accelerator supporting up to 8 MB of VRAM for framebuffer use. It also included a PCI controller and a PLL clock multiplier that raised a 33 MHz external clock to the internal operating frequency.

The memory controller accommodated B-cache sizes ranging between 64 KB and 2 MB, while main memory support extended from 2 MB up to 512 MB. ECC functionality was capable of detecting four-bit errors and correcting single-bit faults. To achieve cost reduction, the system bus width was decreased to 64 bits, which lowered pin count and package dimensions but resulted in roughly a 20% decline in bandwidth and performance—a compromise deemed acceptable for its intended applications.

Containing approximately 1.75 million transistors, the die measured 17.0 by 12.3 mm (209.1 mm2) and was manufactured using the CMOS-4S process at a 0.675 μm feature size with three layers of interconnects. The processor was housed in a sizable 287-pin CPGA package measuring about 57.4 by 57.4 mm.

Alpha 21066A

The Alpha 21066A, internally known as LCA45, is an economical version of the Alpha 21064A announced on November 14, 1994. It debuted with two clock speed options: 100 MHz at $175 per unit and 233 MHz at $360 per unit for orders of 5,000 units, later adding a 266 MHz model.

Mitsubishi Electric provided secondary manufacturing for the 21066A under the designation M36066A, marking its initial production of Alpha microprocessors. Samples running at both 100 MHz and 233 MHz were released concurrently, with commercial shipments scheduled for mid-1995. Pricing for the 233 MHz variant was set at $490 per batch of 1,000 units.

Distinct from the Alpha 21064A, this version omitted the separate 16 KB instruction and data caches but introduced software-adjustable internal clock frequencies to optimize power consumption. Digital implemented various iterations of the 21066A within products that had previously employed the original 21066. Additionally, Tadpole Technology incorporated the 233 MHz model into its ALPHAbook 1 laptop.

The chip contained approximately 1.8 million transistors on a die area of about 161.32 mm2, fabricated using Digital’s CMOS-5 process with a feature size of 0.5 μm. Mitsubishi’s M36066A utilized a comparable three-level-metal process at the same scale.

Alpha 21068

The Alpha 21068 (DECchip 21068) was designed specifically for embedded applications requiring reduced power consumption and cost through lower operating frequencies. Launched in September 1993, it ran at a clock speed of 66 MHz while maintaining a maximum power dissipation of only 9 watts. Initial pricing stood at $221 per unit for orders of five thousand but was later cut by approximately sixteen percent to $186 in July of the following year.

Digital incorporated the Alpha 21068 into its AXPpci 33 motherboard as well as AXPvme single-board computer platforms.

Alpha 21068A

The Alpha 21068A (also known as DECchip 21068A) represents an embedded version of the Alpha 21066A, functioning at a clock speed of 100 MHz.

Chipsets

At the outset, there was no standardized chipset available for the 21064 and 21064A processors, prompting Digital to depend on proprietary ASICs, which increased development expenses for external manufacturers. To mitigate this challenge, Digital launched the DECchip 21070 (referred to as Apecs) chipset tailored for OEM use.

This chipset family consisted of two variants: the DECchip 21071, designed for workstation systems, and the DECchip 21072, intended for high-performance workstations or entry-level uniprocessor servers. The primary distinction between them was in their memory architecture: the 21071 incorporated a 64-bit memory bus supporting parity-protected memory ranging from 8 MB up to 2 GB, whereas the 21072 featured a wider 128-bit bus accommodating ECC-protected memory from 16 MB to 4 GB.

The DECchip 21070 chipset was composed of three key elements: the COMANCHE B cache and memory controller, multiple DECADE data slice chips (two units for the 21071 and four units for the 21072), and the EPIC PCI controller providing a 32-bit interface to the DECADE chips.

Announced on January 10, 1994, with sample units made available immediately and mass production commencing mid-year, pricing was set at $90 per unit for the 21071 and $120 per unit for the 21072 when purchased in quantities of 5,000.

Notable adopters included Carrera Computers with their Pantera workstation line, as well as Digital's own AlphaStation workstations and uniprocessor AlphaServer systems.

References

Further reading

  • "DEC Ventures into Microprocessor Market with Alpha". (4 March 1992). Microprocessor Report, Volume 6, Issue 3.
  • "Introduction of DEC's Alpha Architecture". (4 March 1992). Microprocessor Report, Volume 6, Issue 3.
  • "Digital Announces Extensive Alpha Processor Lineup". (18 November 1992). Microprocessor Report, Volume 6, Issue 3.
  • "Digital Unveils PCI Chipsets for Alpha Processors". (12 July 1993). Microprocessor Report, Volume 7, Issue 9.
  • "Alpha Expands to Entry-Level with Digital's 21066". (13 September 1993). Microprocessor Report, Volume 7, Issue 12.
  • Bhandarkar, Dileep P. (1995). Alpha Architecture and Implementations. Digital Press.
  • Fox, Thomas F. (1994). "Design Strategies for High-Performance Microprocessors at Digital". Proceedings of the 31st Annual ACM-IEEE Design Automation Conference. pp. 586–591.
  • Gronowski, Paul E. et al. (May 1998). "Designing High-Performance Microprocessors". IEEE Journal of Solid-State Circuits 33 (5): pp. 676–686.

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