Alpha 21068A

Digital Equipment Corporation

Company type	Public
Industry	Computer hardware
Founded	November 8, 1957 (1957-11-08)
Headquarters	Maynard, Massachusetts , United States
Products	Alpha 21064 microprocessor, others

The Alpha 21064 is a microprocessor created and manufactured by Digital Equipment Corporation, implementing the Alpha (initially Alpha AXP) instruction set architecture (ISA). Originally launched as the DECchip 21064 before its 1994 renaming, it carried the codename EV4. Announced in February 1992 and reaching mass production by September of the same year, it marked Digital's first commercially available Alpha ISA processor. The Alpha 21064 was later succeeded by the Alpha 21064A in October 1993, which itself was replaced by the Alpha 21164 in 1995.

History

The first Alpha processor prototype was a test chip called EV3, produced using Digital’s 1.0-micrometre CMOS-3 fabrication process. This early version did not include a floating point unit and featured only 1 KB of cache. EV3 served to validate advanced circuit design methods and facilitated firmware and operating system development through simulators and emulators.

The production-ready chip, known as EV4, was manufactured with Digital’s 0.75 μm CMOS-4 technology. The microarchitecture design team included Dirk Meyer, responsible for major functional blocks, and Edward McLellan, who handled issue logic, while Jim Montanaro led the circuit implementation efforts. The EV3 powered the Alpha Demonstration Unit (ADU), a multiprocessor platform used to develop software for the Alpha architecture before EV4’s release.

Introduced at the 39th International Solid-State Circuits Conference in February 1992, the initial 150 MHz samples were priced at $3,375 each for orders exceeding 100 units, with prices dropping to $1,560 per chip when purchasing over 1,000 units. Mass production commenced in September 1992.

By February 1993, the cost of the 150 MHz model had decreased to $1,096 per unit for orders above 1,000 chips. That same month saw the introduction of a 200 MHz variant priced at $3,495 for sample kits and $1,231 per unit for bulk purchases over 10,000 units, with deliveries starting in August 1993. Meanwhile, the price of the 150 MHz version further declined to $853 per unit by July.

Following the release of the Alpha 21066 and 21068 models in September 1993, Digital restructured its product lineup—launching a new 166 MHz version priced at $499 per unit for orders exceeding 5,000 units and reducing the cost of the 150 MHz model to $455.

On June 6, 1994, prices for both the 200 MHz and 166 MHz processors were cut by as much as 31% to better compete with Intel’s Pentium line—resulting in prices of $544 and $404 respectively for purchases over 5,000 units.

Digital Equipment Corporation was the exclusive manufacturer of the Alpha 21064 without any secondary suppliers. Production took place at Digital’s manufacturing plants located in Hudson, Massachusetts and South Queensferry, Scotland.

Users

The Alpha 21064 found primary application in high-performance workstations and servers. Notable adopters included:

• Aspen Systems utilizing it in their Alpine workstation series
• Carrera Computers integrating it into Hercules 150, Hercules 200, and Pantera II workstations
• Cray Research, which implemented the 150 MHz version within their Cray T3D supercomputers
• Digital itself deploying it across entry-level workstations and servers such as DECpc AXP 150, DEC 2000 AXP, DEC 3000 AXP, mid-range DEC 4000 AXP, and high-end DEC 7000/10000 AXP server systems
• Encore Computer incorporating it into their Infinity R/T real-time high-performance computers

Performance

From its launch until 1993, the 21064 held the title of the fastest microprocessor available, a position it retained until IBM introduced the multi-chip POWER2. It continued to be the leading single-chip microprocessor in terms of speed until the release of the 275 MHz 21064A in October 1993.

Description

The Alpha 21064 is a superpipelined, dual-issue superscalar CPU that processes instructions in their original sequence. It can dispatch up to two instructions per clock cycle across four distinct functional units: integer, floating-point (FPU), address, and branch units. The integer pipeline consists of seven stages, while the floating-point pipeline spans ten stages, sharing its initial four stages with the I-box.

I-box

Functioning as the control hub, the I-box handles instruction fetching, decoding, issuing, and pipeline control. During the first stage, it retrieves two instructions from the instruction cache (I-cache). Branch prediction takes place in stage two through either static or dynamic techniques: static prediction assesses the sign bit of branch displacement to assume backward branches as taken; dynamic prediction relies on a branch history table with 2,048 entries, achieving approximately 80% accuracy. A mispredicted branch incurs a penalty of four cycles.

Instruction decoding occurs in stage three. In stage four, the I-box checks resource availability and evaluates instruction pairing options based on integer register file port usage. The 21064 supports pairing combinations such as integer operate with floating-point operate, any load/store with any operate instruction, integer operate with integer branch, or floating-point operate with floating-point branch. However, it disallows pairing between an integer operate and a floating-point store or between a floating-point operate and an integer store. If pairing is not feasible or resources are insufficient, pipeline stages one through four stall until instructions can be issued.

The I-box incorporates two fully associative instruction translation buffers (ITBs) for converting virtual addresses to physical addresses: an eight-entry ITB for 8 KB pages and a four-entry ITB for 4 MB pages. Both employ a not-last used replacement strategy.

Execution

All instructions commence execution at stage five; register file reads happen in stage four. Pipelines beginning at stage five are non-stallable.

Integer unit

The integer unit processes integer instructions and includes the integer register file (IRF) alongside the E-box. The IRF contains thirty-two 64-bit registers equipped with four read ports and two write ports, which are evenly shared between the integer and branch units. The E-box comprises an adder, logic unit, barrel shifter, and multiplier. Except for multiply, shift, and byte manipulation operations, most integer instructions complete by stage five with a latency of one cycle. Shift and byte manipulation instructions have a two-cycle latency due to additional pipeline stages. To conserve die space, the multiplier is non-pipelined, causing multiply instructions to have variable latencies ranging from 19 to 23 cycles. Results from integer operations are written back to the IRF during stage seven.

Address unit

Known as the "A-box," the address unit executes load and store instructions concurrently with the integer unit by utilizing its own displacement adder for calculating virtual addresses instead of relying on the integer unit’s adder. It features a fully associative 32-entry translation lookaside buffer (TLB), called the data translation buffer (DTB), which translates virtual addresses into physical addresses. The 21064 supports a virtual address space of 43 bits (equivalent to 8 TB) and a physical address space of 34 bits (up to 16 GB).

Store operations utilize a write buffer consisting of four entries each holding 32 bytes; this buffer merges adjacent stores and postpones writes to minimize system bus traffic, thereby enhancing load instruction performance.

Floating-point unit

The floating-point unit consists of two main components: the floating-point register file (FRF) and the F-box. The FRF contains thirty-two 64-bit registers, each equipped with three read ports and two write ports. The F-box incorporates a floating-point pipeline alongside a non-pipelined divide unit that completes division operations by retiring one bit per cycle.

During the fourth pipeline stage, the FRF is accessed to read data, which is then decomposed into fraction, exponent, and sign fields. For addition instructions, this stage also begins calculating the exponent difference and predicts normalization. Multiplication instructions generate a 3 × multiplicand product. Stages five and six manage alignment or normalization shifts and compute sticky bits for addition and subtraction operations. The multiplication process employs a pipelined, two-way interleaved array utilizing a radix-8 Booth algorithm. Final addition and rounding take place in stage eight, with floating-point results written back to the FRF at stage ten.

Most floating-point instructions have a pipeline latency of six cycles. Division operations for single-precision and double-precision numbers are handled by the non-pipelined divide unit, requiring 31 and 61 cycles respectively to complete.

Caches

The 21064 integrates two primary on-chip caches: an 8 KB data cache (D-cache) operating with a write-through policy, and an 8 KB instruction cache (I-cache). Both caches are direct-mapped, offer single-cycle access times, and use 32-byte line sizes. They are constructed from six-transistor SRAM cells, each occupying 98 μm². Each cache array measures 1,024 cells in width by 66 cells in height, with the upper two rows reserved for redundancy purposes.

An optional external secondary cache (B-cache) can be added, supporting sizes ranging from 128 KB up to 16 MB. This cache runs at frequencies between one-sixteenth and one-third of the internal clock speed (equivalent to 12.5 to 66.67 MHz at a 200 MHz internal clock). It is direct-mapped with a default line size of 128 bytes and interfaces via the system bus.

External interface

The external interface provides a 128-bit data bus that operates at speeds from one-eighth to one-half of the internal clock frequency (25 to 100 MHz when the internal clock is 200 MHz). The bus width can be configured to support a narrower 64-bit interface if required. Additionally, the interface includes a 34-bit wide address bus.

Fabrication

The 21064 microprocessor contains approximately 1.68 million transistors and was initially manufactured by Digital using their CMOS-4 fabrication process featuring a 0.75 μm technology node and three layers of aluminum interconnects. The original EV4 die measures 13.9 mm by 16.8 mm, totaling an area of 233.52 mm². A subsequent variant, the EV4S, utilizes CMOS-4S technology—a shrink of about 10% in optical dimensions—with a reduced feature size of 0.675 μm and die dimensions of 12.4 mm by 15.0 mm (186 mm²).

Operating on a 3.3-volt power supply, the EV4 dissipates up to 30 watts at its maximum clock rate of 200 MHz. The EV4S version lowers power consumption to a peak of 21 watts at 150 MHz, increasing to as much as 27 watts when running at 200 MHz.

Package

The processor is enclosed within a pin grid array (PGA) package made from alumina ceramic, measuring approximately 61.72 mm square with a total of 431 pins. Of these pins, 291 function as signal lines while the remaining 140 provide power and ground connections. A tungsten heat spreader beneath the package supports direct attachment of the heatsink, which is fastened securely using nuts on studs extending through the package surface.

The Alpha 21064A, also known as the DECchip 21064A and internally referred to as EV45, represents an upgraded iteration of the Alpha 21064, introduced in October 1993. This processor was available at frequencies of 200, 225, 233, 275, and 300 MHz. On July 6, 1994, the 225 MHz version was superseded by the 233 MHz model, which was offered at a unit price of US$788 for orders of 5,000 units—reflecting a 10% cost reduction compared to the previous model. Concurrently, the price of the 275 MHz variant dropped by 25%, reaching US$1,083 per batch of 5,000. The 300 MHz edition was unveiled in October 1995 and became available by December that year. A specialized variant named the 21064A-275-PC was designed exclusively to operate on Windows NT or compatible operating systems.

Serving as Digital's flagship Alpha microprocessor successor, the 21064A powered high-performance systems such as Digital's DEC 3000 AXP, DEC 4000 AXP, and DEC 7000/10000 AXP series. Additionally, it found use in products from Aspen Systems (Alpine workstation), BTG (Action AXP275 RISC PC), Carrera Computers (Cobra AXP 275 workstation), NekoTech (overclocked Mach 2-289-T workstation), and Network Appliance (NetApp) storage solutions.

Enhancements at the microarchitecture level included doubling the primary cache capacity from 8 KB to 16 KB for both instruction and data caches, incorporating parity protection for cache tags and data arrays, reducing floating-point division latency through a faster divider capable of retiring two bits per cycle on average, and upgrading branch prediction accuracy with an expanded two-bit branch history table containing 4,096 entries.

The processor is composed of approximately 2.8 million transistors on a silicon die measuring 14.5 by 10.5 mm (totaling 152.25 mm²), manufactured using Digital’s CMOS-5 fabrication process—a 0.5 μm technology featuring four layers of aluminium interconnects.

Alpha 21066

The Alpha 21066, also called the DECchip 21066 and codenamed LCA4 (Low Cost Alpha), is a cost-effective variant of the Alpha 21064 that debuted in September 1993 with mass production commencing in early 1994. The first model operated at 166 MHz and was priced at US$385 per unit for orders of 5,000 units. A slower version running at 100 MHz targeted embedded system applications; sampling began late in 1994 with volume production starting in the third quarter of 1995. Importantly, it was the pioneer microprocessor to integrate a PCI controller on-chip.

Engineered for budget-conscious markets such as personal computers running Windows NT, Digital utilized various Alpha 21066 models within its Multia client systems, AXPpci OEM motherboards, and AXPvme single-board computers. Other adopters comprised Aspen Systems (Alpine workstation), Carrera Computers (Pantera I workstation), NekoTech (Mach 1-166 PC), and Parsys (TransAlpha TA9000 supercomputers).

Benefiting from process miniaturization, this chip included features tailored for embedded environments: an integrated B-cache alongside a memory controller supporting ECC; a basic graphics accelerator capable of handling up to an 8 MB VRAM framebuffer; a PCI controller; and a phase-locked loop clock generator that multiplied an external clock of 33 MHz to achieve internal operating frequencies.

Its memory controller accommodated B-cache sizes ranging from 64 KB to 2 MB and main memory capacities between 2 MB and 512 MB. The ECC functionality enabled detection of multiple-bit errors while correcting single-bit faults. To minimize expenses, the system bus width was confined to 64 bits—resulting in fewer pins and smaller package size but causing roughly a 20% reduction in bandwidth and performance, which was deemed acceptable for its intended applications.

The Alpha 21066 contains about 1.75 million transistors on a die measuring approximately 17.0 by 12.3 mm (209.1 mm²), fabricated using CMOS-4S technology—a 0.675 μm process with three layers of interconnect—and housed in a CPGA package with dimensions near 57.4 by 57.4 mm featuring 287 pins.

Alpha 21066A

The Alpha 21066A, also known as LCA45, represents a budget-friendly version of the Alpha 21064A, unveiled on November 14, 1994. It was initially offered in 100 MHz and 233 MHz variants, with prices set at $175 and $360 respectively for orders of 5,000 units. Deliveries commenced in March 1995, followed by the release of a 266 MHz model.

Mitsubishi Electric became a secondary manufacturer of the 21066A, producing it under the name M36066A, marking their debut in Alpha processor fabrication. Announced alongside Digital’s versions, Mitsubishi aimed to provide engineering samples by December 1994 and start mass production by September 1995, pricing the 233 MHz chip at $490 for batches of 1,000 units.

In contrast to the 21064A, the 21066A eliminated the 16 KB instruction and data caches but incorporated software-controlled power management features. Digital integrated various iterations of the 21066A into their product lineup as replacements for older 21066 models. Additionally, Tadpole Technology employed the 233 MHz variant within its ALPHAbook 1 laptop.

This processor contained approximately 1.8 million transistors on a die measuring 161.32 mm², fabricated using Digital’s fifth-generation CMOS-5 process with a 0.5 μm feature size. Mitsubishi’s M36066A utilized a comparable manufacturing technique.

Alpha 21068

The Alpha 21068 (DECchip 21068) was designed specifically for embedded applications, closely resembling the 21066 but operating at a lower clock frequency to minimize power usage and reduce costs. Launched in September 1993 with volume shipments beginning in early 1994, it ran at 66 MHz and had a maximum power consumption of 9 watts. Initially priced at $221 for quantities of 5,000 units, Digital reduced its cost by 16% to $186 in July of the following year.

Digital incorporated the Alpha 21068 into its AXPpci 33 motherboard and AXPvme single-board computer platforms.

Alpha 21068A

The Alpha 21068A (DECchip 21068A) serves as an embedded-system derivative of the Alpha 21066A, operating at a clock speed of 100 MHz.

Chipsets

At first, no standardized chipset existed for the 21064 and 21064A processors; instead, Digital utilized custom ASICs to connect these CPUs with system components. To lower costs associated with third-party development and encourage wider OEM adoption of Alpha technology, Digital introduced the DECchip 21070 chipset family (known as Apecs).

The DECchip 21070 lineup included two variants: the DECchip 21071, intended for workstation use, and the DECchip 21072, designed for high-performance workstations or entry-level uniprocessor servers. The primary distinction between these two was memory support—the 21071 featured a narrower, 64-bit memory bus supporting from 8 MB up to 2 GB of parity-protected RAM, while the 21072 offered a broader, 128-bit memory bus accommodating up to 4 GB of ECC-protected memory.

This chipset consisted of three major elements: COMANCHE B-cache/memory controller; DECADE data slice chips—two for the 21071 and four for the larger-scale 21072; and EPIC PCI controller. The DECADE chips implemented data paths in modular slices of 32 bits each, while EPIC provided a PCI interface through a separate dedicated path also sized at 32 bits.

Officially released on January 10, 1994, with samples distributed soon after, volume production began mid-year. Pricing for orders of 5,000 units was set at $90 for the DECchip 21071 and $120 for the DECchip 21072.

Among its customers were Carrera Computers for their Pantera workstation line and Digital itself for certain AlphaStation models as well as uniprocessor AlphaServer systems.

References

• Alpha 21064 and 21064A Microprocessors Hardware Reference Manual, June 1996. Order number: EC-Q92UC-TE. Digital Equipment Corporation.
• Apiki, Steve; Grehan, Rick (March 1995). "Fastest NT Workstations". Byte.
• Bhandarkar, Dileep. "Alpha Implementations" Archived 24 May 2011 at the Wayback Machine, IEEE Computer Society Technical Committee on Computer Architecture Newsletter, December 1995.
• Computergram International (25 February 1992). "DEC Reveals More On Alpha, Challenges Hewlett-Packard's Precision Architecture RISC". Computer Business Review.
• Computergram International (26 February 1992). "DEC Describes Its Alpha RISC, Kubota Discloses Its Plans". Computer Business Review.
• Computergram International (7 June 1994). "DEC slashes Alpha AXP Chip Prices by up to 31%". Computer Business Review.
• Computergram International (13 September 1993). "DEC adds Alphas for Personal Computers, Control". Computer Business Review.
• Computergram International (11 January 1994). "Microprocessor Report's Annual Chip Awards Declare Motorola 88110 the Part least likely to...". Computer Business Review.
• Computergram International (11 November 1994). "Mitsubishi Electric Is Ready To Sample Its First Alpha At Last". Computer Business Review.
• Computergram International (25 November 1994). "Mitsubishi's First Alpha Provides The Same Functionality As DEC's 21066A". Computer Business Review.
• Digital Equipment Corporation (10 January 1994). "Digital Introduces PCI-Based System Logic Chipsets For Alpha AXP 21064 Microprocessors And Announces The Industry's First PCI To PCI Bridge Chip". Press release.
• Dobberpuhl, Daniel W., Witek, Richard T. et al. "A 200-MHz 64-bit Dual-issue CMOS Microprocessor", Digital Technical Journal, Volume 4, Number 4, Special Issue 1992, pp. 35–50.
• Gwennap, Linley (12 September 1994). "Digital Leads the Pack with 21164", Microprocessor Report, Volume 8, Number 12.
• Krause, Reinhardt (13 September 1993). "DEC unveils two Alphas in PCI, embedded drive". Electronic News.
• Krause, Reinhardt (18 October 1993). "DEC readies 225/275MHz Alphas". Electronic News.
• Krause, Reinhardt (21 November 1994). "Alpha partners roll 233MHz 21066A". Electronic News.
• McKinney, Dina L. et al. "Digital's DECchip 21066: The First Cost-focused Alpha AXP Chip". Digital Technical Journal, Volume 6, Number 1, Winter 1994, pp. 66–77.
• McLellan, Edward (June 1993). "The Alpha AXP Architecture and 21064 Processor". IEEE Micro. pp. 36–47.
• Ryan, Bob; Thompson, Tom (January 1994). "RISC Grows Up". Byte.

Further reading

• "DEC Ventures into Microprocessor Market with Alpha". (4 March 1992). Microprocessor Report, Volume 6, Issue 3.
• "Introduction of DEC's Alpha Architecture". (4 March 1992). Microprocessor Report, Volume 6, Issue 3.
• "Digital Announces Extensive Alpha Processor Lineup". (18 November 1992). Microprocessor Report, Volume 6, Issue 3.
• "Digital Unveils PCI Chip Sets for Alpha Processors". (12 July 1993). Microprocessor Report, Volume 7, Issue 9.
• "Alpha Expands to Entry-Level with Digital's 21066". (13 September 1993). Microprocessor Report, Volume 7, Issue 12.
• Bhandarkar, Dileep P. (1995). Alpha Architecture and Implementations. Digital Press.
• Fox, Thomas F. (1994). "Designing High-Performance Microprocessors at Digital". Proceedings of the 31st Annual ACM-IEEE Design Automation Conference. pp. 586–591.
• Gronowski, Paul E. et al. (May 1998). "Design Techniques for High-Performance Microprocessors". IEEE Journal of Solid-State Circuits 33 (5): pp. 676–686.